Memory cell and storage device

Patent metadata

Field	Value
Publication number	US-9740255-B2
Application number	US-201415023066-A
Country	US
Kind code	B2
Filing date	Sep 18, 2014
Priority date	Sep 20, 2013
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A memory cell ( 101 ) is connected to a word line (WL), a bit line (BL), and a power supply line (PL), and includes a flip-flop storing data based on a change in resistance value of a magnetic tunnel junction element, and, a power gating field-effect transistor including a drain that is one end of a current path connected to the power supply line, and which has another end connected to the flip-flop. The ON and OFF states of the power gating field-effect transistor are controlled based on a control signal applied to a control terminal of the power gating field-effect transistor.

First claim

The invention claimed is:

1. A memory cell comprising:
a flip-flop comprising a first inverter and a second inverter, the first inverter comprising a first magnetic tunneling junction element and a first field-effect transistor, the second inverter comprising a second magnetic tunneling junction element and a second field-effect transistor, the first inverter and the second inverter being cross coupled to each other;
a power gating field-effect transistor;
a third field-effect transistor; and
a fourth field-effect transistor,
wherein:
respective pin layers of the first magnetic tunneling junction element and the second magnetic tunneling junction element are connected to a power supply line through the power gating field-effect transistor;
a control terminal of the power gating field-effect transistor is connected to a bit select line;
an output terminal of the first inverter is a node to which a free layer of the first magnetic tunneling junction element and a control terminal of the second field-effect transistor are connected, is grounded through the first field-effect transistor, and is connected to a bit line through the third field-effect transistor;
an output terminal of the second inverter is a node to which a free layer of the second magnetic tunneling junction element and a control terminal of the first field-effect transistor are connected, is grounded through the second field-effect transistor, and is connected to an inverse bit line through the fourth field-effect transistor; and
respective control terminals of the third field-effect transistor and the fourth field-effect transistor are connected to a word line.

2. The memory cell according to claim 1 , wherein, at a time of data writing to the flip-flop, the power gating field-effect transistor is controlled to be an OFF state, and the third field-effect transistor and the fourth field-effect transistor are controlled to be an ON state.

3. The memory cell according to claim 1 , wherein the power supply line is designed as a common line with the word line.

4. The memory cell according to claim 1 , wherein:
the control terminal of the power gating field-effect transistor is connected to the bit select line through a same conductivity-type control field-effect transistor; and
a predetermined voltage is applied to a control terminal of the control field-effect transistor.

5. A storage device comprising the memory cells according to claim 1 ,
wherein:
the memory cells are laid out in a matrix;
a memory cell of the memory cells laid out in the matrix is connected to a word line, a bit line orthogonal to the word line, an inverse bit line orthogonal to the word line, a power supply line in parallel with the word line, and a bit select line orthogonal to the power supply line;
the word line is connected to a plurality of the memory cells in a same row;
the bit line and the inverse bit line are connected to a plurality of the memory cells in a same column;
the power supply line is connected to one end of a current path of a power gating field-effect transistor included in each of the plurality of the memory cells in the same row; and
the bit select line is connected to, directly or through a control field-effect transistor, a control terminal of the power gating field-effect transistor included in each of the plurality of the memory cells in the same column.

6. The storage device according to claim 5 , wherein the power supply line is designed as a common line with the word line.

7. A memory cell comprising:
a flip-flop comprising a first inverter and a second inverter, the first inverter comprising a first magnetic tunneling junction element and a first field-effect transistor, the second inverter comprising a second magnetic tunneling junction element and a second field-effect transistor, the first inverter and the second inverter being cross coupled to each other;
a power gating field-effect transistor;
a third field-effect transistor; and
a fourth field-effect transistor,
wherein:
respective free layers of the first magnetic tunneling junction element and the second magnetic tunneling junction element are connected to a control line through the power gating field-effect transistor;
a control terminal of the power gating field-effect transistor is connected to a bit select line;
an output terminal of the first inverter is a node to which a pin layer of the first magnetic tunneling junction element and a control terminal of the second field-effect transistor are connected, is connected to a power supply terminal through the first field-effect transistor, and is connected to a bit line through the third field-effect transistor;
an output terminal of the second inverter is a node to which a pin layer of the second magnetic tunneling junction element and a control terminal of the first field-effect transistor are connected, is connected to the power supply terminal through the second field-effect transistor, and is connected to an inverse bit line through the fourth field-effect transistor; and
respective control terminals of the third field-effect transistor and the fourth field-effect transistor are connected to a word line.

8. The memory cell according to claim 7 , wherein, at a time of data writing to the flip-flop, the power gating field-effect transistor is controlled to be an OFF state, and the third field-effect transistor and the fourth field-effect transistor are controlled to be an ON state.

9. The memory cell according to claim 7 , wherein the control line is designed as a common line with the word line.

10. The memory cell according to claim 7 , wherein:
the control terminal of the power gating field-effect transistor is connected to the bit select line through a same conductivity-type control field-effect transistor; and
a predetermined voltage is applied to a control terminal of the control field-effect transistor.

11. A storage device comprising the memory cells according to claim 7 ,
wherein:
the memory cells are laid out in a matrix;
a memory cell of the memory cells laid out in the matrix is connected to a word line, a bit line orthogonal to the word line, an inverse bit line orthogonal to the word line, a control line in parallel with the word line, and a bit select line orthogonal to the control line;
the word line is connected to a plurality of the memory cells in a same row;
the bit line and the inverse bit line are connected to a plurality of the memory cells in a same column;
the control line is connected to one end of a current path of a power gating field-effect transistor included in each of the plurality of the memory cells in the same row; and
the bit select line is connected to, directly or through a control field-effect transistor, a control terminal of the power gating field-effect transistor included in each of the plurality of the memory cells in the same column.

12. The storage device according to claim 11 , wherein the control line is designed as a common line with the word line.

13. A memory cell comprising:
a flip-flop comprising a first CMOS inverter, a second CMOS inverter, a first magnetic tunneling junction element and a second magnetic tunneling junction element, the first CMOS inverter comprising a first P-type field-effect transistor and a first N-type field-effect transistor, the second CMOS inverter comprising a second P-type field-effect transistor and a second N-type field-effect transistor;
a power gating field-effect transistor;
a third field-effect transistor; and
a fourth field-effect transistor,
wherein:
respective source terminals of the first P-type field-effect transistor and the second

Assignees

• Univ Tohoku

Inventors

• Ohsawa Takashi
• Endoh Tetsuo

Classifications

• G11C14/0081 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G11C11/1697

  Power supply circuits · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title