Low dropout regulator with replica feedback frequency compensation

Patent metadata

Field	Value
Publication number	US-9740225-B1
Application number	US-201615136792-A
Country	US
Kind code	B1
Filing date	Apr 22, 2016
Priority date	Feb 24, 2016
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Methods, systems, and apparatuses are described for a low dropout voltage regulator that utilizes a replica feedback frequency compensation technique to provide enhanced stability to the low dropout voltage regulator such that the low dropout voltage regulator does not need to be externally compensated with a large capacitor (e.g., larger than 4 microfarads). Rather, a small capacitor (e.g., 4 microfarads or smaller) may be used.

First claim

What is claimed is:

1. A low dropout regulator circuit, comprising:
a first stage having a reference voltage as a first input and a feedback voltage as a second input, the first stage generating a first output voltage;
a second stage configured to receive the first output voltage and to generate a second output voltage;
a third stage configured to receive the second output voltage and to generate a third output voltage, the third output voltage being an output voltage at an output terminal of the low dropout regulator circuit;
a fourth stage configured to receive the second output voltage and to generate a fourth output voltage; and
a feedback stage configured to receive the fourth output voltage and the third output voltage and to generate a feedback voltage that is controlled by a first feedback factor of a main loop and a second feedback factor of a replica feedback frequency compensation (RFFC) loop of the low dropout regulator circuit.

2. The low dropout regulator circuit of claim 1 , wherein the first stage comprises an amplifier having a first input connected to the feedback voltage, a second input connected to the reference voltage, and an output that generates the first output voltage.

3. The low dropout regulator circuit of claim 1 , wherein the second stage comprises a first transistor and a second transistor,
the first transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal of the first transistor being connected to a ground voltage, and the gate terminal of the first transistor being connected to the first output voltage, and
the second transistor having a source terminal, a gate terminal, and a drain terminal, the source terminal of the second transistor being connected to a supply voltage, the drain terminal of the second transistor being connected to the drain terminal of the first transistor, and the gate terminal of the second transistor being connected to the drain terminal of the second transistor and the third stage.

4. The low dropout regulator circuit of claim 3 , wherein the first and second transistors are a pair of complementary metal oxide semiconductor transistors.

5. The low dropout regulator circuit of claim 4 , wherein the first transistor is an n-channel metal oxide semiconductor (nMOS) transistor and the second transistor is a p-channel metal oxide semiconductor (pMOS) transistor.

6. The low dropout regulator circuit of claim 1 , wherein the third stage comprises a transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal being connected to a supply voltage, the drain terminal being connected to the output terminal of the low dropout regulator circuit, and the gate terminal being connected to the second output voltage.

7. The low dropout regulator circuit of claim 6 , wherein the transistor is a p-channel metal oxide semiconductor (pMOS) transistor.

8. The low dropout regulator circuit of claim 1 , wherein the fourth stage comprises a transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal being connected to a supply voltage, the drain terminal being connected to a resistor that has a terminal connected to a ground voltage, and the gate terminal being connected to the second output voltage.

9. The low dropout regulator circuit of claim 8 , wherein the transistor is a p-channel metal oxide semiconductor (pMOS) transistor.

10. The low dropout regulator circuit of claim 1 , wherein the first feedback factor is determined by a first feedback circuit comprising a first resistor, a second resistor, a first capacitor, and a second capacitor, the first and second resistors being connected at a first node and in series between the output terminal of the low dropout regulator circuit and a ground terminal, the first and second capacitors being connected at a second node and in series between the output terminal and the ground terminal, the first node being shorted to the second node.

11. The low dropout regulator circuit of claim 10 , wherein the second feedback factor is determined by the first feedback circuit and another feedback circuit that comprises a third resistor and a third capacitor,
the third resistor being connected to the third capacitor and the ground terminal, and
the third capacitor being connected to the third resistor and the second node.

12. A system, comprising:
a low dropout regulator circuit that comprises
a first stage having a reference voltage as a first input and a feedback voltage as a second input, the first stage generating a first output voltage;
a second stage configured to receive the first output voltage and to generate a second output voltage;
a third stage configured to receive the second output voltage and to generate a third output voltage, the third output voltage being an output voltage at an output terminal of the low dropout regulator circuit;
a fourth stage configured to receive the second output voltage and to generate a fourth output voltage; and
a feedback stage configured to receive the fourth output voltage and the third output voltage and to generate a feedback voltage that is controlled by a first feedback factor of a main loop and a second feedback factor of a replica feedback frequency compensation (RFFC) loop of the low dropout regulator circuit; and

an output capacitor connected to the output terminal of the low dropout regulator circuit.

13. The system of claim 12 , wherein the low dropout regulator circuit is configured to drive loads with a current rating of greater than 500 milliamperes and wherein the output capacitor has a capacitance that is proportional to the current rating.

14. The system of claim 12 , wherein the first stage comprises an amplifier having a first input connected to the feedback voltage, a second input connected to the reference voltage, and an output that generates the first output voltage.

15. The system of claim 12 , wherein the second stage comprises a first transistor and a second transistor,
the first transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal of the first transistor being connected to a ground voltage, and the gate terminal of the first transistor being connected to the first output voltage, and
the second transistor having a source terminal, a gate terminal, and a drain terminal, the source terminal of the second transistor being connected to a supply voltage, the drain terminal of the second transistor being connected to the drain terminal of the first transistor, and the gate terminal of the second transistor being connected to the drain terminal of the second transistor and the third stage.

16. The system of claim 12 , wherein the third stage comprises a transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal being connected to a supply voltage, the drain terminal being connected to the output terminal of the low dropout regulator circuit, and the gate terminal being connected to the second output voltage.

17. The system of claim 12 , wherein the fourth stage comprises a transistor having a source terminal, a drain terminal, and a gate terminal, the source terminal being connected to a supply voltage, the drain terminal being connected to a resistor that has a terminal connected to a ground voltage, and the gate terminal being connected to the second output voltage.

18. The system of claim 12 , wherein the first feedback factor is determined by a first feedback circuit comprising a first resistor, a second resistor, a first c

Assignees

• Avago Technologies General Ip

Inventors

• Wong Kian Tiong

Classifications

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• G05F3/26

  Current mirrors · CPC title

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title

• G05F1/468

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• G05F1/565

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title