Method for testing a signal path

Patent metadata

Field	Value
Publication number	US-9739845-B2
Application number	US-201514872729-A
Country	US
Kind code	B2
Filing date	Oct 1, 2015
Priority date	Oct 1, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A method for testing a signal path of a first IC formed as a monolithically integrated circuit on a semiconductor body together with a magnetic field sensor and has a signal output and a power supply connection and a test mode state and a normal operating state. A power supply of the first IC is switched off, and a signal output is connected with a reference potential, and the power supply of the first IC is switched on and the signal output is disconnected from the reference potential. Subsequently in a test mode state, a self-test is performed in the first IC and a test pattern is configured at the signal output or at the power supply connection and the test pattern is evaluated by the control unit for testing of the signal path.

First claim

What is claimed is:

1. A method for testing a signal path of a first housed IC that forms a monolithically integrated circuit on a semi-conductor body together with a magnetic field sensor and has a signal output and a power supply connection and a test mode state and a normal operating state, wherein, during the normal operating state, an output signal is provided at the signal output, the output signal being dependent on a signal which is tapped at the magnetic field sensor, and a second housed IC is provided that is formed as a control unit, wherein via the control unit, a switch from the normal operating state to the test mode state is performed in the first housed IC, the method comprising:
switching off, in a first step, the power supply of the first IC;
connecting, in a second step, the signal output with a reference potential;
switching on, in a third step, the power supply of the first IC;
disconnecting, in a fourth step, the signal output from the reference potential; and
performing, subsequently in the test mode state, a test of the first IC by the first IC such that a test pattern is configured at the signal output or at the power supply connection and the test pattern is evaluated by the control unit for testing of the signal path.

2. The method for testing a signal path according to claim 1 , wherein between the third step and the fourth step the control unit waits a predetermined time and/or verification whether the power supply of the first IC is stable.

3. The method for testing a signal path according to claim 1 , wherein the magnetic field sensor is interconnected with a current source of the power supply during the test mode state and a predetermined test current is provided to the magnetic field sensor.

4. The method for testing a signal path according to claim 3 , wherein the magnetic field sensor has a plurality of connections and the current source is alternatingly interconnected with different connections of the magnetic field sensor during the test mode state.

5. The method for testing a signal path according to claim 4 , wherein an influence of the magnetic field sensor under test is suppressed via switching.

6. The method for testing a signal path according to claim 1 , wherein the first IC is arranged in a mounting fixture of an end device during testing of the signal path or is interconnected with the second IC in a field application.

7. The method for testing a signal path according to claim 1 , wherein the first IC and the second IC are connected via exactly one two-wire transmission or exactly one three-wire transmission.

8. The method for testing a signal path according to claim 1 , wherein the first IC is switched to the normal operating state without a trigger signal from the second IC after the test of the first IC is completed.

9. The method for testing a signal path according to claim 1 , wherein a current sink and a current source are alternatingly applied to at least one connection of the magnetic field sensor.

10. The method for testing a signal path according to claim 1 , wherein an offset voltage applied to the magnetic field sensor is determined by the control unit during the test mode state.

11. The method for testing a signal path according to claim 1 , wherein the reference potential is configured as a ground potential or as a power supply potential.

12. The method for testing a signal path according to claim 1 , wherein the magnetic field sensor is a hall plate.

Assignees

• Micronas Gmbh
• Tdk-Micronas Gmbh

Inventors

• Muthers David
• Ritter Joachim
• Wagner Michael
• Von Ehr Markus
• Kauter Thomas

Classifications

• G01R33/07 Primary

  Hall effect devices · CPC title

• G01R35/00

  Testing or calibrating of apparatus covered by the other groups of this subclass · CPC title