Persistence filtering in spd arrays
US-2024406582-A1 · Dec 5, 2024 · US
US9739660B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9739660-B2 |
| Application number | US-201514802401-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 17, 2015 |
| Priority date | Mar 9, 2015 |
| Publication date | Aug 22, 2017 |
| Grant date | Aug 22, 2017 |
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A circuit configured to amplify a signal from which an offset is cancelled includes an amplifier including an input stage configured to receive an input signal, the amplifier configured to amplify the input signal and output the amplified signal, and a switch including a transistor configured to reset the amplifier in response to a reset signal, the transistor including a body node connecting the transistor to the circuit, the transistor being configured to form a current path between the body node of the transistor and the input stage of the amplifier.
Opening claim text (preview).
What is claimed is: 1. A circuit configured to amplify a signal from which an offset is cancelled, the circuit comprising: an amplifier comprising an input stage configured to receive an input signal, the amplifier configured to amplify the input signal and output the amplified signal; and a switch comprising a transistor configured to reset the amplifier in response to a reset signal, the transistor comprising a body node connecting the transistor to the circuit; wherein the transistor is configured to form a current path between the body node of the transistor and the input stage of the amplifier. 2. The circuit of claim 1 , wherein: the amplifier comprises an output stage configured to output the amplified signal, and the body node is connected to the output stage of the amplifier. 3. The circuit of claim 2 , wherein: the transistor further comprises a source node and a drain node; and the switch further comprises: a diode connected between the source node and the drain node of the transistor, and a resistance component connected between the source node and the drain node of the transistor. 4. The circuit of claim 2 , wherein the transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor comprising a drain node connected to the input stage, a gate node configured to receive the reset signal, and a source node connected to the output stage. 5. The circuit of claim 1 , wherein the amplifier comprises a PMOS transistor comprising a source node connected to a supply voltage, a gate node configured to receive the input signal, and a drain node configured to output an output signal corresponding to the amplified signal. 6. The circuit of claim 1 , wherein the transistor comprises a floating well, and the body node is connected to the floating well of the transistor. 7. The circuit of claim 6 , wherein: the transistor further comprises a source node and a drain node; the switch further comprises: a first diode connected to the floating well and the source node of the transistor, and a second diode connected to the floating well and the drain node of the transistor, and wherein the first diode and the second diode are connected in series and in opposite directions to each other. 8. The circuit of claim 1 , further comprising a power source configured to supply a bias power to the amplifier and the transistor. 9. The circuit of claim 1 , wherein the amplifier comprises an output stage configured to output the amplified signal, and wherein the circuit further comprises: a first capacitor connected to the input stage of the amplifier; and a second capacitor connected to the output stage of the amplifier. 10. A circuit configured to amplify a signal from which noise is reduced, the circuit comprising: an amplifier configured to amplify an input signal, the amplifier comprising an input stage configured to receive the input signal and an output stage configured to output the amplified signal; a switch comprising a transistor configured to reset the amplifier in response to a reset signal; and a first diode configured to form a current path between the input stage and the output stage of the amplifier so that a leakage current generated by the amplifier flows through the current path. 11. The circuit of claim 10 , wherein the first diode is connected between the input stage and the output stage of the amplifier. 12. The circuit of claim 10 , further comprising a second diode located along the current path and having an opposite polarity to the first diode. 13. The circuit of claim 10 , wherein the transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor comprising a drain node connected to the input stage, a gate node configured to receive the reset signal, a source node connected to the output stage, and a body node connected to a supply voltage. 14. The circuit of claim 10 , wherein the amplifier comprises a PMOS transistor comprising a source node connected to a supply voltage, a gate node configured to receive the input signal, and a drain node configured to output an output signal corresponding to the amplified signal. 15. The circuit of claim 10 , further comprising: a power source configured to supply a bias power to the amplifier, the switch and the first diode. 16. An event-based vision sensor comprising: a sensing element configured to sense an event, wherein the sensing element comprises: an event detector configured to detect an occurrence of the event and generate an input signal based on the detected occurrence; a difference amplifier configured to amplify the input signal; and an event signal generator configured to generate an event signal corresponding to the amplified signal by processing the amplified signal, wherein the difference amplifier comprises: an input terminal configured to receive the input signal and an output terminal configured to output the amplified signal, and a switch configured to reset the difference amplifier in response to a reset signal, the switch comprising a node connecting the switch to the sensing element, and wherein the switch is configured to form a current path between the input terminal and the output terminal of the difference amplifier by a connection between the output terminal and the node. 17. The event-based vision sensor of claim 16 , wherein the event detector comprises: a photodiode configured to output a current corresponding to a change in an intensity of light received by the photodiode, in response to receiving the light; and a converter configured to convert the current to the input signal in the form of a voltage. 18. The event-based vision sensor of claim 16 , wherein the event signal generator is configured to generate the event signal based on a result of a comparison between the amplified signal and a predetermined threshold. 19. The event-based vision sensor of claim 16 , wherein the current path comprises: a diode connected between the input terminal and the output terminal; and a resistance component connected between the input terminal and the output terminal.
A voltage generating circuit being realised for biasing different circuit elements · CPC title
Photodiode · CPC title
Electric circuits {(for command of an exposure part G03B7/02)} · CPC title
with FET's (H03F3/085 takes precedence) · CPC title
using a switching device (H03F1/305, H03F3/005, H03F3/38 take precedence) · CPC title
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