Frequency synthesizer with dynamic phase and pulse-width control

Patent metadata

Field	Value
Publication number	US-9735787-B2
Application number	US-201514741984-A
Country	US
Kind code	B2
Filing date	Jun 17, 2015
Priority date	Mar 18, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

First claim

What is claimed is:

1. A frequency synthesizer, comprising:
a count circuit configured to adjust a stored count value by an adjustment value based at least in part on a count clock signal and adjust the stored count value to a reset value based at least in part on the stored count value satisfying a count threshold, wherein the reset value corresponds to a difference between the stored count value and the count threshold in response to the stored count value satisfying the count threshold; and
an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the reset value,
wherein the count circuit is further configured to alter at least one of a period or phase of the output clock signal based at least in part on modifying a rollover rate of the count circuit.

2. The frequency synthesizer of claim 1 , wherein modifying the rollover rate comprises modifying the count threshold.

3. The frequency synthesizer of claim 1 , wherein the count circuit is further configured to determine the reset value in response to the stored count value exceeding the count threshold.

4. The frequency synthesizer of claim 1 , wherein the count circuit comprises:
accumulator logic configured to generate a plurality of output words that identify a timing of the rising and falling edges in the output clock signal.

5. The frequency synthesizer of claim 4 , wherein the output clock generator is further configured to:
receive a reference clock, the reference clock having a higher frequency than the count clock signal input to the count circuit;
select a transition in the reference clock based at least in part on the output words; and
generate a rising or falling edge in the output clock signal based at least in part on the timing of the selected transition in the reference clock.

6. The frequency synthesizer of claim 1 , wherein the count circuit is a first count circuit, the stored count value is a first stored count value, the adjustment value is a first adjustment value, the reset value is a first reset value, the count threshold is a first count threshold, and the rollover rate is a first rollover rate and wherein the frequency synthesizer further comprises:
a second count circuit configured to adjust a second stored count value by a second adjustment value based at least in part on the count clock signal and adjust the second stored count value to a second reset value based at least in part on the second stored count value satisfying a second count threshold, wherein the second reset value corresponds to a difference between the second stored count value and the second count threshold in response to the second stored count value satisfying the second count threshold,
wherein the output clock generator is further configured to generate the output clock signal having rising and falling edges that are based at least in part on the second reset value, and
wherein a timing of a second rollover rate of the second count circuit is offset from that of the count circuit.

7. The frequency synthesizer of claim 6 , wherein the count circuit is further configured to generate a plurality of output words via a logical exclusive OR of the first and second stored count values, wherein the output clock generator is further configured to generate the output clock signal based at least in part on the output words.

8. The frequency synthesizer of claim 1 , wherein the count circuit is further configured to generate a plurality of output words based on the stored count value, wherein the output clock generator further comprises a phase interpolator configured to reorganize the output words into sequential order, the output clock generator further configured to generate the rising and falling edges in the output words based at least in part on the reorganized output words.

9. The frequency synthesizer of claim 8 , wherein the count circuit is further configured to generate at least one of gapped-periodic, on-demand n-shot, or pseudo-random signals in the output clock signal based at least in part on the output words.

10. The frequency synthesizer of claim 6 , wherein the first and second count circuits are further configured to alter a pulse-width of the output clock signal based at least in part on modifying the first and second rollover rates.

11. A frequency synthesizer, comprising:
a count circuit configured to modify a stored count value by an adjustment value; and
an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold,
wherein the count circuit is further configured to alter at least one of a period or phase of the output clock signal based at least in part on dynamically modifying the count threshold of the count circuit.

12. The frequency synthesizer of claim 11 , wherein the adjustment value is a positive and fixed value, the count circuit further being configured to reset the stored count value when the count threshold is satisfied, the count threshold being satisfied in response to the stored count value being greater than the count threshold.

13. The frequency synthesizer of claim 12 , wherein the count circuit is further configured to:
determine a reset value based at least in part on a difference between the stored count value and the count threshold in response to the count threshold being satisfied; and
reset the stored count value to the reset value in response to the count threshold being satisfied.

14. The frequency synthesizer of claim 11 , wherein the count circuit comprises:
an accumulator configured to: i) receive a count clock and ii) increment the stored count value for each period of the count clock; and
an accumulator logic circuit configured to generate a plurality of output words that identify a timing of the rising and falling edges in the output clock signal.

15. The frequency synthesizer of claim 14 , wherein the output clock generator is further configured to:
receive a reference clock, the reference clock having a higher frequency than the count clock;
select a transition in the reference clock based at least in part on the output words; and
generate the rising and falling edges in the output clock signal based at least in part on the timing of the selected transition in the reference clock.

16. The frequency synthesizer of claim 11 , wherein the count circuit is a first count circuit, the stored count value is a first stored count value, the adjustment value is a first adjustment value, the count threshold is a first count threshold, and wherein the frequency synthesizer further comprises:
a second count circuit configured to modify a second stored count value by a second adjustment value,
wherein the output clock generator is further configured to generate the output clock signal having rising and falling edges that are based at least in part on the second stored count value satisfying a second count threshold.

17. A method of synthesizing an output clock signal, comprising:
modifying a count value, stored by a count circuit, by an adjustment value;
generating an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold; and
altering at least one of a period or phase of the output clock signal via dynamically modifying the count threshold of the count circuit.

18. The method of claim 17 , wherein altering at least one of a period or phase of the output

Assignees

• Analog Devices Inc

Inventors

• Burbano Oscar Sebastian
• Mcshea Matthew D
• Derounian Peter
• Nelson Reuben P
• Zheng Ziwei
• Jeffries Brad P

Classifications

• H03L7/18 Primary

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03K23/662

  by adding or suppressing pulses · CPC title

• G06F1/022 Primary

  Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers (G06F1/025, G06F1/03 take precedence) · CPC title

• H03K23/665

  by presetting · CPC title

• H03K23/58

  Gating or clocking signals not applied to all stages, i.e. asynchronous counters (H03K23/74 - H03K23/84 take precedence) · CPC title