Transistor manufacturing method and transistor

US9735380B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9735380-B2
Application numberUS-201615154160-A
CountryUS
Kind codeB2
Filing dateMay 13, 2016
Priority dateNov 21, 2013
Publication dateAug 15, 2017
Grant dateAug 15, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A transistor manufacturing method includes: forming a first insulator layer of which formation material is a fluorine-containing resin, on a substrate having a source electrode, a drain electrode, and a semiconductor layer so as to cover the semiconductor layer; forming a second insulator layer so as to cover the first insulator layer; forming a base film on at least part of a surface of the second insulator layer; and after depositing a metal which is an electroless plating catalyst on a surface of the base film, forming a gate electrode on the surface of the base film by electroless plating, wherein the forming of the base film is performed by applying a liquid substance which is a formation material of the base film to the surface of the second insulator layer, and the second insulator layer has a higher lyophilic property with respect to the liquid substance than the first insulator layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A transistor manufacturing method comprising: forming a first insulator layer of which formation material is a fluorine-containing resin, on a substrate on which a source electrode, a drain electrode, and an organic semiconductor layer that comes into contact with surfaces of the source electrode and the drain electrode are formed so as to cover the organic semiconductor layer; forming a second insulator layer so as to cover the first insulator layer; forming a plating base film on at least part of a surface of the second insulator layer; and after depositing a metal which is an electroless plating catalyst on a surface of the plating base film, forming a gate electrode on the surface of the plating base film by electroless plating, wherein the forming of the plating base film is performed by applying a liquid substance which is a formation material of the plating base film to the surface of the second insulator layer, and the second insulator layer has a higher lyophilic property with respect to the liquid substance than the first insulator layer. 2. The transistor manufacturing method according to claim 1 , wherein the forming of the first insulator layer is performed by applying a solution including the fluorine-containing resin and a fluorine-containing solvent that dissolves the fluorine-containing resin, on a surface of the organic semiconductor layer. 3. The transistor manufacturing method according to claim 1 , wherein in the forming of the first insulator layer, the first insulator layer is formed so as to entirely cover the an upper surface and a lateral surface of the organic semiconductor layer. 4. The transistor manufacturing method according to claim 1 , wherein the liquid substance includes a silane coupling agent, and the silane coupling agent includes a group having at least one of a nitrogen atom and a sulfur atom. 5. The transistor manufacturing method according to claim 4 , wherein the silane coupling agent has an amino group. 6. The transistor manufacturing method according to claim 5 , wherein the silane coupling agent is a primary amine or a secondary amine. 7. The transistor manufacturing method according to claim 1 , wherein the liquid substance includes a solution in which a resin material is dissolved and a filler that is dispersed in the solution. 8. The transistor manufacturing method according to claim 1 , wherein the substrate is made of a non-metallic material. 9. The transistor manufacturing method according to claim 8 , wherein the substrate is made of a resin material. 10. The transistor manufacturing method according to claim 9 , wherein the substrate has flexibility. 11. A transistor comprising: a substrate on which a source electrode and a drain electrode are formed; a semiconductor layer that comes into contact with surfaces of the source electrode and the drain electrode; a first insulator layer that is provided so as to cover the semiconductor layer; a second insulator layer that is provided so as to cover the first insulator layer; a plating base film that is provided on at least part of a surface of the second insulator layer; and a gate electrode that is provided on a surface of the plating base film, wherein a formation material of the first insulator layer is a fluorine-containing resin, and the second insulator layer has a higher lyophilic property with respect to an organic solvent than the first insulator layer. 12. The transistor according to claim 11 , wherein the plating base film includes a silane coupling agent, and the silane coupling agent includes a group having at least one of a nitrogen atom and a sulfur atom. 13. The transistor according to claim 11 , wherein the plating base film includes a resin film and a filler that is dispersed in the resin film. 14. The transistor according to claim 11 , wherein the semiconductor layer is an organic semiconductor layer. 15. The transistor according to claim 11 , which is formed on a substrate that is made of a non-metallic material. 16. The transistor according to claim 15 , wherein the substrate is made of a resin material. 17. The transistor according to claim 16 , wherein the substrate has flexibility.

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What does patent US9735380B2 cover?
A transistor manufacturing method includes: forming a first insulator layer of which formation material is a fluorine-containing resin, on a substrate having a source electrode, a drain electrode, and a semiconductor layer so as to cover the semiconductor layer; forming a second insulator layer so as to cover the first insulator layer; forming a base film on at least part of a surface of the se…
Who is the assignee on this patent?
Nikon Corp
What technology area does this patent fall under?
Primary CPC classification H01L51/0529. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 15 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).