Access devices to correlated electron switch

Patent metadata

Field	Value
Publication number	US-9735360-B2
Application number	US-201514979086-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Dec 22, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

First claim

What is claimed is:

1. A method comprising:
forming one or more first layers comprising a metal oxide to provide a correlated electron switch (CES); and
forming one or more second layers between a third layer and the one or more first layers to provide a first access device to the CES, wherein the third layer comprises a metal layer to provide a first terminal of the CES.

2. The method of claim 1 , and further comprising forming one or more fourth layers between a fifth layer and the one or more first layers to provide a second access device to the CES, wherein the fifth layer comprises a metal layer to provide a second terminal of the CES.

3. The method of claim 1 , wherein the one or more second layers are n-type doped or p-type doped.

4. The method of claim 1 , wherein the third layer is formed over the one or more second layers.

5. The method of claim 1 , wherein the one or more second layers comprises a metal oxide.

6. The method of claim 1 , wherein the one or more second layers comprises a polysilicon.

7. A device comprising:
one or more first layers comprising a metallic oxide comprising a correlated electron switch (CES);
one or more terminals;
one or more second layers formed between a first terminal of the one or more terminals and the one or more first layers to form a first access device to the CES; and
one or more third layers formed between a second terminal of the one or more terminals to form a second access device to the CES.

8. The device of claim 7 , wherein the CES is responsive to application of a first voltage across the one or more first metallic layers while maintaining a first current through the one or more first layers to place the CES in a high impedance or insulative state;
wherein the CES is responsive to application of a second voltage across the one or more first layers while maintaining a second current through the one or more first layers to place the memory state of the CES element in a low impedance or conductive state; and
wherein the state of the CES element is detectable based, at least in part, on a measured current through the access device in response to application of a third voltage across the one or more first layers.

9. The device of claim 1 , wherein the one or more first layers are separated from the one or more second layers by a first metallic layer, and wherein the one or more first layers are separated from the one or more third layers by a second metallic layer.

10. The device of claim 1 , wherein the one or more first layers are p-type doped, wherein the one or more second layers are n-type doped, and wherein the one or more third layers comprise a correlated electron material in an intrinsic state.

11. The device of claim 1 , wherein the one or more first layers are p-type doped, and wherein the one or more second layers and the one or more third layers comprise a correlated electron material in an intrinsic state.

12. The device of claim 1 , wherein the one or more first layers comprise a correlated electron material in an intrinsic state, and wherein the one or more second layers and the one or more third layers are n-type doped.

13. The device of claim 1 , wherein the first access device comprises a P/N junction diode, a Schottky barrier diode, a metal-insulator-metal (MIM) diode, a tunnel diode or a varistor, or a combination thereof.

14. The device of claim 7 , wherein the one or more first layers and the one or more second layers are formed from a correlated electron material (CEM), and wherein the one or more first layers are p-type doped.

15. The device of claim 7 , wherein the device comprises a correlated electron random access memory (CeRAM) element in a crosspoint memory array.

16. The device of claim 7 , wherein the first layer is p-type doped, wherein the second and third layers are n-type doped.

17. The device of claim 14 , wherein the one or more second metallic oxide layers comprise the CEM in an intrinsic state.

18. The device of claim 7 , wherein the one or more second layers comprises zinc oxide doped with bismuth.

19. The device of claim 14 , wherein the one or more second layers are n-type doped.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Shifren Lucian
• Paz De Araujo Carlos Alberto

Classifications

• H01L29/93

  Electricity · mapped topic

• H01L27/0808

  Electricity · mapped topic

• H01L49/003 Primary

  Electricity · mapped topic

• H10D1/64

  Variable-capacitance diodes, e.g. varactors · CPC title

• H10D84/215

  of only varactors · CPC title