Array substrate, display panel and method of manufacturing thin film transistor

Patent metadata

Field	Value
Publication number	US-9735278-B2
Application number	US-201514744557-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Oct 27, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

An array substrate, a display panel and a method of manufacturing a thin film transistor (TFT) are provided. The array substrate includes a base substrate and a thin film transistor (TFT) formed on the base substrate, and the TFT includes a gate electrode, a gate insulating layer, an active layer, source/drain electrodes and an interlayer insulating layer. The source/drain electrodes include a first electrode and a second electrode, and the interlayer insulating layer is located between the first electrode and the second electrode. The gate electrode, the gate insulating layer and the active layer are arranged sequentially in a direction perpendicular to a thickness direction of the array substrate, and the first electrode, the interlayer insulating layer and the second electrode are arranged sequentially in the thickness direction of the array substrate.

First claim

The invention claimed is:

1. An array substrate, comprising: a base substrate and a thin film transistor (TFT) formed on the base substrate, the TFT comprising a gate electrode, a gate insulating layer, an active layer, source/drain electrodes and an interlayer insulating layer,
wherein, the source/drain electrodes comprise a first electrode and a second electrode, and the interlayer insulating layer is located between the first electrode and the second electrode; the gate electrode, the gate insulating layer and the active layer are arranged sequentially in a direction perpendicular to a thickness direction of the array substrate; the first electrode, the interlayer insulating layer and the second electrode are located at a side of the active layer away from the gate insulating layer; the first electrode, the interlayer insulating layer and the second electrode are arranged sequentially in the thickness direction of the array substrate, and the second electrode is located at a side of the first electrode away from the base substrate of the array substrate,
wherein a thickness direction of each of the gate electrode, the gate insulating layer and the active layer is continuously perpendicular to the thickness direction of the array substrate.

2. The array substrate according to claim 1 , wherein, one of the first electrode and the second electrode is a drain electrode, and the other one of the first electrode and the second electrode is a source electrode.

3. The array substrate according to claim 1 , wherein, a size of the gate electrode, the gate insulating layer and the active layer measured in a direction parallel to the thickness direction of the array substrate is greater than that measured in the direction perpendicular to the thickness direction of the array substrate.

4. The array substrate according to claim 3 , wherein, a sum of sizes of the first electrode, the second electrode and the interlayer insulating layer measured in the direction parallel to the thickness direction of the array substrate is substantially equivalent to the size of the active layer measured in the direction parallel to the thickness direction of the array substrate.

5. A display panel, comprising the array substrate according to claim 1 .

6. The display panel according to claim 5 , wherein, one of the first electrode and the second electrode is a drain electrode, and the other one of the first electrode and the second electrode is a source electrode.

7. The display panel according to claim 5 , wherein, a size of the gate electrode, the gate insulating layer and the active layer measured in a direction parallel to the thickness direction of the array substrate is greater than that measured in the direction perpendicular to the thickness direction of the array substrate.

8. The display panel according to claim 7 , wherein, a sum of sizes of the first electrode, the second electrode and the interlayer insulating layer measured in the direction parallel to the thickness direction of the array substrate is substantially equivalent to the size of the active layer measured in the direction parallel to the thickness direction of the array substrate.

9. A method of manufacturing a thin film transistor (TFT), comprising:
forming a pattern of a gate electrode on a base substrate;
forming a pattern of a gate insulating layer at a side of the gate electrode in a direction perpendicular to a thickness direction of the base substrate;
forming a pattern of an active layer at a side of the gate insulating layer away from the gate electrode in the direction perpendicular to the thickness direction of the base substrate;
forming a pattern of a first electrode at a side of the active layer away from the gate electrode in the direction perpendicular to the thickness direction of the base substrate;
forming a pattern of an interlayer insulating layer at a side of the first electrode away from the base substrate in the thickness direction of the base substrate; and
forming a pattern of a second electrode at a side of the insulating layer away from the first electrode in the thickness direction of the base substrate,
wherein a thickness direction of each of the gate electrode, the gate insulating layer and the active layer is continuously perpendicular to the thickness direction of the base substrate.

10. The manufacturing method according to claim 9 , wherein, forming the pattern of the gate electrode on the base substrate comprises:
forming a gate metal layer on the base substrate, and forming the pattern of a gate line and the pattern of the gate electrode by a patterning process.

11. The manufacturing method according to claim 10 , wherein, forming the pattern of the gate insulating layer at the side of the gate electrode in the direction perpendicular to the thickness direction of the base substrate comprises:
forming a gate insulating material layer on the pattern of the gate line and the pattern of the gate electrode, and forming a hollowed area for disposing the first electrode, the second electrode and the interlayer insulating layer at a side of the gate electrode in the direction perpendicular to the thickness direction of the base substrate by a patterning process, and forming a portion of the gate insulating material layer located between the gate electrode and the hollowed area into the pattern of the gate insulating layer.

12. The manufacturing method according to claim 11 , wherein, the first electrode is a source electrode and the second electrode is a drain electrode, and the step of forming the pattern of the first electrode at the side of the active layer away from the gate electrode in the direction perpendicular to the thickness direction of the base substrate comprises:
forming a data metal layer on the gate insulating layer, and forming the pattern of a data line and the pattern of the source electrode by a patterning process.

13. The manufacturing method according to claim 12 , wherein, the step of forming the pattern of the interlayer insulating layer at the side of the first electrode away from the base substrate in the thickness direction of the base substrate comprises:
forming a passivation layer on the pattern of the data line and the pattern of the source electrode, and forming a portion of the passivation layer in the hollowed area into the interlayer insulating layer.

14. The manufacturing method according to claim 12 , wherein, a sum of sizes of the first electrode, the second electrode and the interlayer insulating layer measured in the direction parallel to the thickness direction of the array substrate is substantially equivalent to a size of the active layer measured in the direction parallel to the thickness direction of the array substrate.

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Wang Wu
• Qiu Haijun
• Shang Fei
• Wang Guolei

Classifications

• H01L27/1222

  Electricity · mapped topic

• H01L29/78642 Primary

  Electricity · mapped topic

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title