Light emitting device

Patent metadata

Field	Value
Publication number	US-9735199-B2
Application number	US-201615092682-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	Dec 6, 2012
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A light emitting device includes a substrate, light emitting cells, each of the light emitting cells including a light emitting structure including lower and upper semiconductor layers, an upper electrode, and a lower electrode, a conductive interconnection layer electrically connecting a lower electrode of a first one of the light emitting cells and an upper electrode of a second one of the light emitting cells, and a current blocking layer disposed to extend from between the upper electrode and the upper semiconductor layer, wherein each light emitting cell further includes a conductive layer arranged to electrically connect the upper electrode of the second light emitting cell to the upper semiconductor layer of the second light emitting cell.

First claim

What is claimed is:

1. A light emitting device, comprising:
a substrate;
first and second light emitting cells spaced apart from one another on the substrate, each including:
a light emitting structure including:
lower and upper semiconductor layers, conductive types of the lower and upper semiconductor layers being different from each other;
an active layer provided between the lower and upper semiconductor layers;
an upper electrode on the upper semiconductor layer;
a lower electrode on the lower semiconductor layer; and
a conductive layer on the upper semiconductor layer;
a conductive interconnection layer configured to electrically connect a lower electrode of the first light emitting cell and an upper electrode of the second light emitting cell; and
a current blocking layer provided so as to extend from between the upper electrode of the second light emitting cell and the upper semiconductor layer of the second light emitting cell, and provided between the light emitting structure of the second light emitting cell and the conductive interconnection layer to electrically separate the conductive interconnection layer from the light emitting structure of the second light emitting cell,
wherein the conductive layer extends from between the upper electrode of the second light emitting cell and the current blocking layer to on the upper semiconductor layer of the second light emitting cell and is configured to electrically connect the upper electrode of the second light emitting cell to the upper semiconductor layer of the second light emitting cell,
wherein the upper electrode of the second light emitting cell, the lower electrode of the first light emitting cell, and the conductive interconnection layer are formed as an integration layer, and
wherein the integration layer includes an adhesive layer and a bonding layer that overlap each other, a reflection layer not being provided between the adhesive layer and the bonding layer.

2. The light emitting device according to claim 1 , wherein the upper electrode of the second light emitting cell has a lower surface facing the upper semiconductor layer of the second light emitting cell,
wherein the upper semiconductor layer of the second light emitting cell has a top surface facing the upper electrode of the second light emitting cell, and
wherein the current blocking layer is provided between the lower surface of the upper electrode and the top surface of the upper semiconductor layer.

3. The light emitting device according to claim 1 , wherein the current blocking layer is provided between the lower semiconductor layer of the first light emitting cell and the conductive interconnection layer, and between the substrate and the conductive interconnection layer.

4. The light emitting device according to claim 2 , wherein the current blocking layer provided between the upper electrode and the upper semiconductor layer of the second light emitting cell has an upper surface facing the upper electrode, and
wherein the upper surface of the current blocking layer has an area that is equal to or greater than an entire area of the lower surface of the upper electrode.

5. The light emitting device according to claim 1 , wherein the integration layer has a lower surface facing the upper semiconductor layer of the second light emitting cell,
wherein the current blocking layer provided between the integration layer and the upper semiconductor layer of the second light emitting cell has an upper surface facing the integration layer, and
wherein the upper surface of the current blocking layer has an area that is equal to or greater than an entire area of the lower surface of the integration layer.

6. The light emitting device according to claim 1 , wherein the conductive layer provided on the upper semiconductor layer has an area that is equal to or less than an area of an upper portion of the upper semiconductor layer.

7. The light emitting device according to claim 1 , wherein the conductive layer is formed as a single layer or multiple layers using at least one of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), aluminum tin oxide (ATO), gallium zinc oxide (GZO), IrO x , RuO x , RuO x /ITO, Ni, Ag, Ni/IrO x Au, or Ni/IrO x /Au/ITO.

8. The light emitting device according to claim 1 , wherein the current blocking layer includes an electrically insulating material.

9. The light emitting device according to claim 8 , wherein the current blocking layer has a distributed Bragg reflector.

10. The light emitting device according to claim 9 , wherein the distributed Bragg reflector includes first and second layers having different indexes of refraction alternately stacked at least once and an insulating material.

11. The light emitting device according to claim 1 , wherein the integration layer further includes a barrier layer provided between the adhesive layer and the bonding layer.

12. The light emitting device according to claim 1 , wherein the first and second light emitting cells are connected in series by the conductive interconnection layer.

13. The light emitting device according to claim 1 , wherein the first and second light emitting cells are spaced apart from one another in a horizontal direction, and
wherein the conductive interconnection layer, the upper electrode, the conductive layer, and the current blocking layer overlap one another in a vertical direction.

14. A light emitting device, comprising:
substrate;
a plurality of light emitting cells provided to be spaced apart from one another on the substrate, each of the light emitting cells including:
a light emitting structure including:
lower and upper semiconductor layers, conductive types of the lower and upper semiconductor layers being different from each other;
an active layer provided between the lower and upper semiconductor layers;
an upper electrode disposed on the upper semiconductor layer;
a lower electrode disposed on the lower semiconductor layer; and
a conductive layer on the upper semiconductor layer;
a conductive interconnection layer configured to electrically connect a lower electrode of a first one of adjacent light emitting cells and an upper electrode of a second one of the adjacent light emitting cells; and
a current blocking layer provided between the light emitting structure of the second one of the adjacent light emitting cells and the conductive interconnection layer to electrically separate the conductive interconnection layer from the light emitting structure of the second one of the adjacent light emitting cells,
wherein the current blocking layer includes:
a first portion provided between a bottom surface of the upper electrode and a top surface of the upper semiconductor layer of the second light emitting cell; and
a second portion extending from the first portion to between the adjacent light emitting cells and the conductive interconnection layer,
wherein the conductive layer is configured to electrically connect the upper electrode of the second one of the adjacent light emitting cells and the upper semiconductor layer of the second one of the adjacent light emitting cells,
wherein the upper electrode of the second one of the adjacent light emitting cells, the lower electrode of the first one of the adjacent light emitting cells, and the conductive interconnection layer are formed as an integration layer, and
wherein the integration layer includes an adhesive layer and a bonding layer that overlap e

Assignees

• Lg Innotek Co Ltd

Inventors

• Choi Byung Yeon
• Kim Myeong Soo
• Beom Hee Young
• Lee Yong Gyeong
• Ju Hyun Seoung
• Hong Gi Seok

Classifications

• H01L2924/0002

  Electricity · mapped topic

• H01L33/62

  Electricity · mapped topic

• H01L33/145

  Electricity · mapped topic

• H01L33/10

  Electricity · mapped topic

• H01L27/15

  Electricity · mapped topic