TFT flat sensor and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-9735183-B2
Application number	US-201414550040-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Sep 19, 2012
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method of manufacturing a thin film transistor flat sensor that includes depositing a first metal film on a substrate and forming a common electrode on the substrate with one patterning process; successively depositing an insulating film and a second metal film on the substrate having the common electrode formed thereon, and forming a gate electrode by applying one pattering process to the second metal film; applying one patterning process to the deposited insulating film to form a common electrode insulating layer, wherein a first via hole is formed in the common electrode insulating layer at a location corresponding to the common electrode; depositing a transparent conductive film on the substrate having the common electrode, and forming a first conductive film layer, acting as one polar plate of a storage capacitor, on the common electrode and the gate electrode with one patterning process.

First claim

What is claimed is:

1. A manufacturing method for a thin film transistor (TFT) flat sensor comprising:
depositing a first metal film on a substrate and forming a common electrode on the substrate with a first patterning process;
successively depositing an insulating film and a second metal film on the substrate having the common electrode formed thereon, and forming a gate electrode by applying a second patterning process to the second metal film;
applying a third patterning process to the deposited insulating film to form a common electrode insulating layer, wherein a first via hole is formed in the common electrode insulating layer at a location corresponding to the common electrode;
depositing a transparent conductive film on the substrate having the common electrode, the common electrode insulating layer and the gate electrode formed thereon, and forming a first conductive film layer, acting as one polar plate of a storage capacitor, on the common electrode and the gate electrode with a fourth patterning process;
the method further comprising:
successively forming a gate insulating layer, an active layer, a second conductive film layer acting as another polar plate of the storage capacitor, a drain electrode and a source electrode, a protection layer, and a third conductive film layer for collecting carriers on the substrate having the first conductive film layer formed thereon,
wherein the second conductive file layer is provided between the active layer and the source electrode, and a second via hole is formed in the protection layer at a location correspondinq to the source electrode.

2. The method of claim 1 , wherein forming of the common electrode on the substrate comprises:
forming the common electrode on the substrate in a net-like wiring manner.

3. The method of claim 1 , wherein the first conductive film layer has a first part on the common electrode and a second part on the gate electrode, the first part contacts the common electrode, the second part contacts the gate electrode, the first part does not contact the second part, and the second part is enwrapped on an external surface of the gate electrode.

4. The method of claim 1 , wherein the protection layer comprises a passivation layer and a resin layer located between the passivation layer and the third conductive film layer.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Xu Shaoying
• Xie Zhenyu
• Chen Xu

Classifications

• H01L31/145

  Electricity · mapped topic

• H01L29/4908

  Electricity · mapped topic

• H01L27/14658

  Electricity · mapped topic

• H01L27/1214

  Electricity · mapped topic

• H01L27/12

  Electricity · mapped topic