Method to match SOI transistors using a local heater element

Patent metadata

Field	Value
Publication number	US-9735172-B2
Application number	US-201615003927-A
Country	US
Kind code	B2
Filing date	Jan 22, 2016
Priority date	Nov 3, 2010
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.

First claim

What is claimed is:

1. A process of forming an SOI integrated circuit, comprising the steps:
forming a first transistor and a second transistor in said SOI integrated circuit where said first transistor and said second transistor form a matched transistor pair;
forming a first matching resistance heater coupled to said first transistor but not the second transistor so as to alter the threshold voltage of the first transistor; and
forming a second matching resistance heater coupled to said second transistor but not the first transistor so as to alter the threshold voltage of the second transistor.

2. A process of forming an SOI integrated circuit, comprising the steps:
forming a first transistor and a second transistor in said SOI integrated circuit where said first transistor and said second transistor form a matched transistor pair;
forming a first matching resistance heater coupled to said first transistor; and
forming a second matching resistance heater coupled to said second transistor, wherein said step of forming a first matching resistance heater further comprises the steps:
forming a diffusion in contact with at least one of a source and a drain of said first transistor where a doping of said diffusion is opposite to the doping of said source and said drain;
doping said diffusion;
blocking silicide from a diode between said diffusion and said at least one of said source and said drain; and
blocking silicide from a center portion of said diffusion to form a resistor body of said first matching resistance heater.

3. The process of claim 2 where said SOI transistor is nmos and said resistor is p-type single crystal silicon with a resistivity between 100 ohms and 10 kohms.

4. The process of claim 1 where said step of forming a first matching resistance heater further comprises the steps:
forming a polysilicon resistor geometry at the same time a gate geometry of said first transistor formed and over an active geometry of said first transistor and adjacent to at least one of a source and a drain said first transistor;
doping said polysilicon resistor geometry to a desired resistivity; and
blocking silicide formation over a body of said polysilicon resistor geometry.

5. The process of claim 4 , wherein said SOI transistor is nmos and said polysilicon resistor has a resistivity between 100 ohms and 10 kohms.

6. The process of claim 1 where said step of forming a first matching resistance heater further comprises the steps:
forming a polysilicon resistor geometry which overlies a gate geometry of said SOI transistor;
doping said polysilicon resistor geometry to a desired resistivity; and
blocking silicide formation over a body of said polysilicon resistor geometry.

7. The process of claim 6 , wherein said polysilicon resistor has a resistivity between 100 ohms and 10 kohms.

Assignees

• Texas Instruments Inc

Inventors

• Marshall Andrew

Classifications

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10P32/302

  Doping polycrystalline silicon or amorphous silicon layers · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10W40/10

  Arrangements for heating · CPC title

• H01L2924/00

  Electricity · mapped topic