Semiconductor integrated circuit device and a method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9735168-B2
Application number	US-201615358950-A
Country	US
Kind code	B2
Filing date	Nov 22, 2016
Priority date	Apr 18, 2002
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a main surface;
a first gate electrode formed over the main surface of the semiconductor substrate;
a first insulating film having a first thickness, the first insulating film being formed between the first electrode and the semiconductor substrate;
a second gate electrode formed over the main surface of the semiconductor substrate;
a second insulating film having a second thickness, the second insulating film being formed between the second gate electrode and semiconductor substrate, and the second gate electrode being disposed along the first gate electrode;
a third insulating film having a third thickness, the third insulating film being formed between the first and second gate electrodes, and the first and second gate electrodes being comprised of a gate of a FET;
a first semiconductor region formed in the main surface of the semiconductor substrate at one side of the gate of the FET; and
a second semiconductor region formed in the main surface of the semiconductor substrate at another side of the gate of the FET;
wherein each of the first and second gate electrodes includes a metal silicide film formed on a top surface thereof,
wherein the first insulating film includes a charge accumulation layer and insulating layers formed on an upper side and a lower side of the charge accumulation layer,
wherein the third thickness is greater than the first thickness, and
wherein the metal silicide film on the first gate electrode and the metal silicide film on the second gate electrode are spaced apart from each other by the third insulating film.

2. The semiconductor device according to the claim 1 ,
wherein the first gate electrode is comprised of a memory gate electrode having a first height,
wherein the second gate electrode is comprised of a control gate electrode having a second height, and
wherein the first height is higher than the second height.

3. The semiconductor device according to the claim 1 , wherein a metal silicide film is formed on each of the first and second semiconductor regions.

4. The semiconductor device according to the claim 1 , wherein the third insulating film comprises a silicon oxide film and a silicon nitride film.

5. The semiconductor device according to the claim 1 , wherein the charge accumulation layer comprises a silicon nitride film.

6. The semiconductor device according to the claim 1 , wherein the second gate electrode is disposed at a sidewall surface of the first gate electrode.

7. The semiconductor device according to the claim 1 , wherein the metal silicide film on the first gate electrode and the metal silicide film on the second gate electrode are formed of the same film.

Assignees

• Renesas Electronics Corp

Inventors

• Shukuri Shoji

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H01L27/11573

  Electricity · mapped topic

• H01L29/42328

  Electricity · mapped topic

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title