Semiconductor device and semiconductor device manufacturing method

Patent metadata

Field	Value
Publication number	US-9735110-B2
Application number	US-99820209-A
Country	US
Kind code	B2
Filing date	Sep 25, 2009
Priority date	Sep 26, 2008
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A semiconductor device according to the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a compressive stress film and a tensile stress film.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a first etching stopper film formed on the semiconductor substrate;
a first wiring layer formed on the first etching stopper film;
a first trench being within the first etching stopper film and the first wiring layer;
a diffusion preventing/etching stopper film;
an interlayer dielectric film formed on the diffusion preventing/etching stopper film, the interlayer dielectric film having a multilayer structure including compressive stress layers made of SiO 2 and tensile stress layers made of SiN, all of every compressive stress layer of the multilayer structure being thicker than all of every tensile stress layer of the multilayer structure;
a second etching stopper film formed on the interlayer dielectric film;
a second wiring layer formed on the second etching stopper film;
a second trench being within the second etching stopper film and the second wiring layer, the second trench opposed to the first trench through the interlayer dielectric film;
a first wire disposed in the first trench; and
a second wire disposed in the second trench; and
a plurality of vias, provided in via holes passing through the interlayer dielectric film, for electrically connecting the first wire and the second wire with each other,
wherein the first wire and the second wire each have an outermost diameter larger than that of the vias.

2. The semiconductor device according to claim 1 , wherein
the multilayer structure has the tensile stress layers and the compressive stress layers laminated alternately and repetitively.

3. The semiconductor device according to claim 1 , wherein
the tensile stress layers have etching selectivity with respect to the compressive stress layers.

4. The semiconductor device according to claim 1 , further comprising:
a first coil made of a wire formed in a same wiring layer as the first wire; and
a second coil made of a wire formed in a same wiring layer as the second wire.

5. The semiconductor device according to claim 4 , wherein the first coil and the second coil constitute a transformer.

6. The semiconductor device according to claim 1 , wherein the interlayer dielectric film has a thickness of more than 5 μm.

7. The semiconductor device according to claim 3 , wherein the multilayer structure has the tensile stress layers and the compressive stress layers laminated alternately and repetitively.

8. The semiconductor device according to claim 4 , wherein the semiconductor substrate, the first coil, the interlayer dielectric film and the second coil are disposed in that stated order along a straight line.

9. The semiconductor device according to claim 1 , wherein the tensile stress layers have etching selectivity with respect to the compressive stress layers so that the tensile stress layers are configured to serve as an etching stopper when the compressive stress layers are etched.

10. The semiconductor device according to claim 4 , wherein
the first coil and the second coil are made of a metallic material containing Cu, and
the tensile stress layer is made of a material having a barrier property against Cu.

11. The semiconductor device according to claim 1 , further comprising:
a barrier metal,
wherein the via holes pass through the compressive stress layers,
wherein the first wire is free of direct physical contact with the second wire,
further wherein the second wire is provided on a side of the interlayer dielectric film that is opposite the side of the interlayer dielectric film that the first wire is provided upon,
further wherein the vias have the barrier metal interposed therebetween.

12. A semiconductor device comprising:
a semiconductor substrate;
a first etching stopper film formed on the semiconductor substrate;
a first wiring layer formed on the first etching stopper film;
a first trench being within the first etching stopper film and the first wiring layer;
a diffusion preventing/etching stopper film;
an interlayer dielectric film formed on the diffusion preventing/etching stopper film, the interlayer dielectric film having a multilayer structure including compressive stress layers made of SiO 2 and tensile stress layers made of SiN, all of every compressive stress layer being thicker than all of every tensile stress layer;
a second etching stopper film formed on the interlayer dielectric film;
a second wiring layer formed on the second etching stopper film;
a second trench being within the second etching stopper film and the second wiring layer, the second trench opposed to the first trench through the interlayer dielectric film;
a first wire disposed in the first trench; and
a second wire disposed in the second trench; and
a plurality of vias, provided in via holes passing through the interlayer dielectric film, for electrically connecting the first wire and the second wire with each other,
wherein the first wire and the second wire each have an outermost diameter larger than that of the vias, and
the tensile stress layers and the compressive stress layers are laminated alternately and repetitively.

13. A semiconductor device comprising:
a semiconductor substrate;
a first etching stopper film formed on the semiconductor substrate;
a first wiring layer formed on the first etching stopper film;
a first trench being within the first etching stopper film and the first wiring layer;
a diffusion preventing/etching stopper film;
an interlayer dielectric film formed on the diffusion preventing/etching stopper film, the interlayer dielectric film having a multilayer structure including compressive stress layers made of SiO 2 and tensile stress layers made of SiN, all of every compressive stress layer of the multilayer structure being thicker than all of every tensile stress layer of the multilayer structure;
a second etching stopper film formed on the interlayer dielectric film;
a second wiring layer formed on the second etching stopper film;
a second trench being within the second etching stopper film and the second wiring layer, the second trench opposed to the first trench through the interlayer dielectric film;
a first wire disposed in the first trench;
a second wire disposed in the second trench; and
a plurality of vias, provided in via holes passing through the interlayer dielectric film, for electrically connecting the first wire and the second wire with each other,
wherein the first wire and the second wire each have an outermost diameter larger than that of the vias, and
in a sectional view, the first wire has a same shape and size as the second wire.

Assignees

• Nakagawa Ryosuke
• Nakao Yuichi
• Rohm Co Ltd

Inventors

• Nakagawa Ryosuke
• Nakao Yuichi

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H10W20/47 Primary

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title