Method and system for asynchronous die operations in a non-volatile memory

Patent metadata

Field	Value
Publication number	US-9734911-B2
Application number	US-201313826848-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Dec 31, 2012
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may program data in a maximum unit of programming for a single memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

First claim

We claim:

1. A mass storage memory system, comprising:
an interface adapted to receive data from a host system;
a plurality of memory die, wherein the plurality of memory die are arranged in respective groups and each respective group is connected to a respective one of a plurality of control channels; and
a controller in communication with the interface and the plurality of memory die over the plurality of control channels, the controller configured to:
in response to receiving a first request from the host system, read or write data fully in parallel in a portion of the plurality of memory die connected to different ones of the plurality of control channels; and
in response to receiving a second request from the host system, read or write data independently and asynchronously with concurrent operations in different memory die in a same one of the plurality of control channels.

2. The mass storage memory system of claim 1 , wherein the controller is configured to manage data writes in an amount equal to a maximum unit of programming for an individual one of the plurality of memory die.

3. The mass storage memory system of claim 2 , wherein the controller is configured to select a memory die within which to write received data based on criteria independent of a host logical block address (LBA) of the received data.

4. The mass storage memory system of claim 3 , wherein the criteria comprises a memory die having a shortest pending data write queue.

5. The mass storage memory system of claim 3 , wherein at least one of the plurality of memory die comprises:
a plurality of layers, each layer having a plurality of memory blocks, wherein a first layer comprises a first bit-per-cell data capacity and a second layer comprises a second bit-per-cell capacity that is greater than the first bit-per-cell capacity; and
a plurality of partitions in each of the plurality of layers, wherein each programmed memory block in the plurality of memory blocks in a layer is exclusively classified as being in a respective one of the plurality of partitions.

6. The mass storage memory system of claim 5 , wherein the controller is configured to identify a data type associated with received data from the host system and to select a memory die based on a number of outstanding transactions for the identified data type.

7. The mass storage memory system of claim 5 , wherein the controller is configured to select a memory die which has a lowest logical fullness within which to write received data.

8. The mass storage memory system of claim 2 , wherein the controller comprises a plurality of controllers and each of the plurality of controllers is only in communication with a respective different one of the plurality of control channels.

9. The mass storage memory system of claim 8 , wherein each of the plurality of controllers is configured to manage data associated with a respective predetermined unique host logical block address (LBA) range.

10. The mass storage memory system of claim 9 , wherein each of the plurality of controllers is configured to independently select a memory die connected to its respective control channel for writing received data independently of each other of the plurality of controllers.

11. A method of managing data comprising:
in a mass storage memory system having an interface adapted to receive data from a host system, a plurality of memory die arranged in respective groups where each respective group is connected to a respective one of a plurality of control channels, and a controller in communication with the interface and the plurality of memory die, the controller:
in response to receiving a first request from the host system, reading or writing data fully in parallel in a portion of the plurality of memory die over multiple control channels of the plurality of control channels; and
in response to receiving a second request from the host system, reading or writing data independently and asynchronously with concurrent operations in different memory die in a same one of the plurality of control channels.

12. The method of claim 11 , further comprising the controller managing data writes in an amount equal to a maximum unit of programming for an individual one of the plurality of memory die.

13. The method of claim 11 , further comprising the controller selecting a memory die within which to write received data based on criteria independent of a host logical block address (LBA) of the received data.

14. The method of claim 13 , wherein the criteria comprises a memory die having a shortest pending data write queue.

15. The method of claim 13 , wherein at least one of the plurality of memory die comprises:
a plurality of layers, each layer having a plurality of memory blocks, wherein a first layer comprises a first bit-per-cell data capacity and a second layer comprises a second bit-per-cell capacity that is greater than the first bit-per-cell capacity; and
a plurality of partitions in each of the plurality of layers, wherein each programmed memory block in the plurality of memory blocks in a layer is exclusively classified as being in a respective one of the plurality of partitions; and
wherein the controller interleaves copying of previously stored data between layers with writing of received host data.

16. The method claim 15 , further comprising the controller:
identifying a data type associated with received data from the host system; and
selecting a memory die based on a number of outstanding transactions for the identified data type.

17. The method of claim 15 , further comprising the controller selecting a die within which to write received data based on a lowest logical fullness in the plurality of memory die.

18. The method of claim 12 , wherein the controller comprises a plurality of controllers, and each of the plurality of controllers is only in communication with a respective single one of the plurality of control channels, wherein the method further comprises:
receiving at each of the plurality of controllers only data associated with a respective predetermined unique host logical block address (LBA) range.

19. The method of claim 18 , further comprising each of the plurality of controllers independently selecting a die connected to its respective control channel for writing received data independently of each other of the plurality of controllers.

20. A mass storage memory system, comprising:
an interface adapted to receive data from a host system;
a plurality of control channels;
a plurality of flash memory die, the plurality of flash memory die being divided into groups, wherein each group is connected to only a respective one of the plurality of control channels; and
a plurality of controllers, each of the plurality of controllers connected to a respective one of the plurality of control channels and in communication with the interface, wherein each respective controller is configured to:
write data independently and asynchronously with concurrent operations in each of the plurality of flash memory die on the respective one of the plurality of control channels connected to the respective controller; and
select, for a write operation, a die connected to its respective control channel independently of each other of the plurality of controllers.

Assignees

• Sinclair Alan Welsh
• Thomas Nicholas James
• Wright Barry
• Sandisk Technologies Llc

Inventors

• Sinclair Alan Welsh
• Thomas Nicholas James
• Wright Barry

Classifications

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G06F3/0613

  in relation to throughput · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title