Systems and methods for individually configuring dynamic random access memories sharing a common command access bus

Patent metadata

Field	Value
Publication number	US-9734890-B1
Application number	US-201615142306-A
Country	US
Kind code	B1
Filing date	Apr 29, 2016
Priority date	Feb 15, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

First claim

What is claimed is:

1. A method for operating a dynamic random access memory (DRAM) device in a personal computing device (PCD), the method comprising:
providing a command decoder, a mode register block, and a multipurpose command (MPC) buffer in the DRAM in the DRAM device, all in communication with a decoder of the DRAM device;
receiving information at the MPC buffer via a data (DQ) bus unique to the DRAM device, the information sent from outside the DRAM device;
providing the received information from the MPC buffer to the decoder;
determining with the decoder based on the received information whether to mask mode register writes (MRW) for the DRAM device;
responsive to the determination, sending a mask signal from the decoder to the command decoder if the determination is to mask the MRW for the DRAM device;
receiving a first MRW at the command decoder via a shared command access (CA) bus, the first MRW sent from outside the DRAM device; and
responsive to an instruction from the decoder:
if the instruction was to mask MRW, ignoring the first MRW at the command decoder, and
if the instruction was to not mask MRW, forwarding the first MRW from the command decoder to the mode register block.

2. The method of claim 1 , wherein the first DRAM device comprises a first die of a multi-die DRAM memory.

3. The method of claim 1 , wherein the method further comprises:
prior to receiving the information at the MPC buffer via the unique DQ bus, receiving a first command at the command decoder via the shared CA bus, the first command including enable information; and
responsive to the received enable information, sending an enable signal to the decoder to cause the decoder to be become active.

4. The method of claim 3 , wherein the enable information comprises an MRW received at the command decoder via the shared CA bus.

5. The method of claim 1 , wherein the MPC buffer comprises a first-in-first-out (FIFO) buffer and the information received at the MPC buffer of the DRAM device comprises a MPC command.

6. The method of claim 5 , wherein the MPC command includes a masking bit and the determination by the decoder is based on a setting of the masking bit.

7. The method of claim 1 , wherein the decoder comprises a phase detector and the information received at the MPC buffer of the DRAM device comprises a DQS pulse.

8. The method of claim 7 , wherein the determination by the decoder is based on a phase of the DQS pulse.

9. The method of claim 1 , wherein sending the mask signal from the decoder to the command decoder further includes instructing the command decoder to mask only the first MRW.

10. The method of claim 1 , wherein sending the mask signal from the decoder to the command decoder further includes instructing the command decoder to mask MRW until a second mask signal is received at the command decoder.

11. A dynamic random access memory (DRAM) device computer system for use in a computing device (PCD), the DRAM device comprising:
a command decoder coupled to a shared command access (CA) bus;
a mode register block in communication with the command decoder;
a multipurpose command (MPC) buffer coupled to a data (DQ) bus unique to the DRAM device; and
a decoder in communication with the command decoder, mode register block, and MPC buffer,
wherein the MPC buffer is configured to receive information from outside the DRAM device over the unique DQ bus and provide the received information to the decoder, the decoder is configured to determine based on the received information whether to mask mode register writes (MRW) for the DRAM device and responsive to the determination send a mask signal to the command decoder if the determination is to mask the MIRW for the DRAM device, and the command decoder is configured to receive from outside the DRAM device a first MRW via the shared CA bus, and responsive to an instruction from the decoder:
if the instruction was to mask MRW, ignore the first MRW, and
if the instruction was to not mask MRW, forward the first MRW to the mode register block.

12. The system of claim 1 , wherein the first DRAM device comprises a first die of a multi-die DRAM memory.

13. The system of claim 12 , wherein the command decoder is further configured to:
receive a first command via the shared CA bus prior to the information being received at the MPC buffer via the unique DQ bus, the first command including enable information, and
responsive to the received enable information, send an enable signal to the decoder to cause the decoder to become active.

14. The system of claim 13 , wherein the first command comprises a MRW and the enable information comprises an enable bit of the MRW.

15. The system of claim 11 , wherein the MPC buffer comprises a first-in-first-out (FIFO) buffer and the information received at the MPC buffer of the DRAM device comprises a MPC command.

16. The system of claim 15 , wherein the MPC command includes a masking bit and the determination by the decoder is based on a setting of the masking bit.

17. The system of claim 11 , wherein the decoder comprises a phase detector and the information received at the MPC buffer of the DRAM device comprises a DQS pulse.

18. The system of claim 17 , wherein the determination by the decoder is based on a phase of the DQS pulse.

19. The system of claim 11 , wherein the mask signal from the decoder to the command decoder includes an instruction to mask only the first MRW.

20. The system of claim 11 , wherein the mask signal from the decoder to the command decoder includes an instruction to mask MRW until a second mask signal is received at the command decoder.

21. A computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method for operating a dynamic random access memory (DRAM) device in a personal computing device (PCD), the method comprising:
providing a command decoder, a mode register block, and a multipurpose command (MPC) buffer in the DRAM in the DRAM device, all in communication with a decoder of the DRAM device;
receiving information at the MPC buffer via a data (DQ) bus unique to the DRAM device, the information sent from outside the DRAM device;
providing the received information from the MPC buffer to the decoder;
determining with the decoder based on the received information whether to mask mode register writes (MRW) for the DRAM device;
responsive to the determination, sending a mask signal from the decoder to the command decoder if the determination is to mask the MRW for the DRAM device;
receiving a first MRW at the command decoder via a shared command access (CA) bus, the first MRW sent from outside the DRAM device; and
responsive to an instruction from the decoder:
if the instruction was to mask MRW, ignoring the first MRW at the command decoder, and
if the instruction was to not mask MRW, forwarding the first MRW from the command decoder to the mode register block.

22. The computer program product of claim 21 , wherein the first DRAM device comprises a first die of a multi-die DRAM memory.

23. The computer program product of claim 21 , wherein the method further comprises:
prior to receiving the information at the MPC buffer via the unique DQ bus, receiving a first command at the command decoder via the shared CA bus, the first command including enable information; and
responsive to

Assignees

• Qualcomm Inc

Inventors

• Aquil Farrukh
• Drop Michael
• Srinivas Vaishnav
• Clovis Philip

Classifications

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G11C11/4082

  Address Buffers; level conversion circuits · CPC title

• G06F13/1678

  using bus width · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title