Systems and methods for individually configuring dynamic random access memories sharing a common command access bus

Patent metadata

Field	Value
Publication number	US-9734878-B1
Application number	US-201615142316-A
Country	US
Kind code	B1
Filing date	Apr 29, 2016
Priority date	Feb 15, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

First claim

What is claimed is:

1. A method for configuring dynamic random access memory (DRAM) in a personal computing device (PCD), the method comprising:
providing a shared command access (CA) bus in communication with a first DRAM device and a second DRAM device;
receiving at the first DRAM device a first command from a system on a chip (SoC) in communication with the first DRAM device and the second DRAM device;
determining with a decoder of the first DRAM device whether to mask a mode register write (MRW) for the first DRAM device in response to the first command received from the SoC;
receiving at the first DRAM device and the second DRAM device via the shared CA bus, a second command from the SoC containing configuration information, wherein the second command comprises the MRW; and
responsive to the determination by the decoder,
if the determination was to mask the received MRW, ignoring the second command at the first DRAM device, and
if the determination was to not mask the received MRW, executing the second command by the first DRAM device.

2. The method of claim 1 , wherein the first DRAM device comprises a first die of a DRAM memory and the second DRAM device comprises a second die of the DRAM memory.

3. The method of claim 2 , wherein the first die and the second die each have an 8 bit input/output width.

4. The method of claim 1 , wherein the first command from the SoC is received via the shared CA bus.

5. The method of claim 4 , wherein the first command comprises the MRW.

6. The method of claim 1 , wherein the first command from the SoC is received at the first DRAM device via a unique data (DQ) bus for the first DRAM device.

7. The method of claim 6 , wherein the first command comprises a multi-purpose command (MPC) write.

8. The method of claim 1 , wherein determining with the decoder of the first DRAM device whether to mask the MRW for the first DRAM device comprises:
receiving data at the first DRAM device over the unique DQ bus for the first DRAM device;
determining with the decoder of the first DRAM device to mask the MRW based on the received data; and
sending a signal from the decoder to a command decoder of the first DRAM device to mask the MRW.

9. The method of claim 8 , wherein the data received at the first DRAM device over the unique DQ bus for the first DRAM device comprises a DQS pulse.

10. The method of claim 8 , further comprising:
receiving at the second DRAM device the first command from the SoC;
determining with a second decoder of the second DRAM device whether to mask the MRW for the second DRAM device in response to the first command received from the SoC; and
responsive to the determination by the second decoder,
if the determination was to mask the received MRW, ignoring the second command at the second DRAM device, and
if the determination was to not mask the received MRW, executing the second command by the second DRAM device.

11. A computer system for a computing device (PCD), the system comprising:
a system on a chip (SoC);
a first DRAM device in communication with the SoC over a first unique data (DQ) bus and over a shared command access (CA) bus, the first DRAM device including a first decoder; and
a second DRAM device in communication with the SoC over a second unique DQ bus and over the shared CA bus,
the first DRAM device configured to:
receive a first command from the SoC,
determine with the first decoder whether to mask a mode register write (MRW) for the first DRAM device in response to the first command received from the SoC,
receive via the shared CA bus, a second command from the SoC containing configuration information, wherein the second command comprises the MRW, and
responsive to the determination by the first decoder, ignore the second command if the determination was to mask the received MRW and execute the second command if the determination was to not mask the received MRW.

12. The system of claim 11 , wherein the first DRAM device comprises a first die of a DRAM memory and the second DRAM device comprises a second die of the DRAM memory.

13. The system of claim 12 , wherein the first die and the second die each have an 8 bit input/output width.

14. The system of claim 11 , wherein the first command from the SoC is received at the first DRAM via the shared CA bus.

15. The system of claim 14 , wherein the first command comprises the MRW.

16. The system of claim 11 , wherein the first command from the SoC is received at the first DRAM device via the first unique DQ.

17. The system of claim 16 , wherein the first command comprises a multi-purpose command (MPC) write.

18. The system of claim 11 , wherein the first DRAM is further configured to:
receive data at the first DRAM device over the unique DQ bus;
determine with the first decoder to mask the MRW based on the received data; and
send a signal from the first decoder to a command decoder of the first DRAM device to mask the MRW.

19. The system of claim 18 , wherein the data received at the first DRAM device over the first unique DQ bus device comprises a DQS pulse.

20. The system of claim 18 , wherein the second DRAM is configured to:
receive the first command from the SoC,
determine with the second decoder whether to mask the MRW for the second DRAM device in response to the first command received from the SoC, and
receive via the shared CA bus, the second command from the SoC containing the configuration information, and
responsive to the determination by the second decoder, ignore the second command if the determination was to mask the received MRW and execute the second command if the determination was to not mask the received MRW.

21. A computer program product comprising a non-transitory computer usable medium having a computer readable program code embodied therein, said computer readable program code adapted to be executed to implement a method for configuring dynamic random access memory (DRAM) in a personal computing device (PCD), the method comprising:
identifying a shared command access (CA) bus in communication with a first DRAM device and a second DRAM device;
receiving at the first DRAM device a first command from a system on a chip (SoC) in communication with the first DRAM device and the second DRAM device;
determining with a decoder of the first DRAM device whether to mask a mode register write (MRW) for the first DRAM device in response to the first command received from the SoC;
receiving at the first DRAM device and the second DRAM device via the shared CA bus, a second command from the SoC containing configuration information, wherein the second command comprises the MRW; and
responsive to the determination by the decoder,
if the determination was to mask the received MRW, ignoring the second command at the first DRAM device, and
if the determination was to not mask the received MRW, executing the second command by the first DRAM device.

22. The computer program product of claim 21 , wherein the first DRAM device comprises a first die of a DRAM memory and the second DRAM device comprises a second die of the DRAM memory.

23. The computer program product of claim 22 , wherein the first die and the second die each have an 8 bit input/output width.

24. The computer program product of claim 21 , wherein the first command from the SoC is received via the shared CA bus.

25. The computer program product of claim 24 , wherein the first command

Assignees

• Qualcomm Inc

Inventors

• Aquil Farrukh
• Drop Michael
• Srinivas Vaishnav
• Clovis Philip

Classifications

• G06F13/1678

  using bus width · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title