Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock

Patent metadata

Field	Value
Publication number	US-9734877-B2
Application number	US-201113312929-A
Country	US
Kind code	B2
Filing date	Dec 6, 2011
Priority date	Dec 13, 2006
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method of operating a memory interface circuit involves selectively operating the memory interface in either a synchronous mode or an asynchronous mode, the synchronous mode controlled by a first clock signal; in asynchronous mode, controlling an address latch for latching an address of a memory location in a memory array, the address latch controlled by an asynchronous address control signal synchronized to a second clock signal that is faster than a third clock signal used to operate the memory array.

First claim

What is claimed is:

1. A memory interface circuit configured to operate in either a synchronous mode or an asynchronous mode, operate in sync with a first clock signal in the synchronous mode, and operate in response to an asynchronous address control signal when operating in the asynchronous mode, the memory interface circuit comprising:
an address interface logic including an address latch and an address register, the address interface is configured to:
control the address latch and the address register for an address of a memory location in a memory array,
respond to the asynchronous address control signal to latch the address in the address latch when operating in the asynchronous mode, and
respond to the first clock signal and not to the asynchronous address signal to register the address in the address register when operating in the synchronous mode; and

a control signal logic configured to:
selectively forward a selected signal, wherein the selected signal includes the first clock signal in the synchronous mode or the asynchronous address control signal in the asynchronous mode,
synchronize the selected signal to a second clock signal, wherein the second clock signal is faster than a third clock signal used to operate the memory array, and
generate a separately applied signal to stabilize an output of the memory array.

2. The memory interface circuit of claim 1 , wherein the address interface logic further comprises an address multiplexer configured to selectively output the contents of the address latch or the contents of the address register, depending on the operating mode.

3. The memory interface circuit of claim 1 , further comprising:
a data interface logic to control, using the asynchronous data control signal synchronized to the second clock signal, a data latch for data output from the memory location in the asynchronous mode.

4. The memory interface circuit of claim 3 , further comprising:
the asynchronous data control signal synchronized to the second clock signal using a one-shot circuit.

5. The memory interface circuit of claim 3 , the data interface logic to control the data latch configured to:
cause the data latch to open as early as possible to accept data output from the memory location, and cause the data latch to close in sync with the second clock.

6. The memory interface circuit of claim 1 , further configured to:
access the memory array in the synchronous mode during a first time period and access the memory array in the asynchronous mode during a second time period, wherein the second time period being distinct from the first time period.

7. The memory interface circuit of claim 1 , further configured to:
access a plurality of memory arrays, access in the synchronous mode a first memory array of the plurality of memory arrays, and access in the asynchronous mode a second memory array of the plurality of memory arrays.

8. The memory interface circuit of claim 1 , further comprising:
a FIFO chain configured to propagate the first clock signal or the asynchronous address control signal in synchronization with the second clock signal.

9. The memory interface circuit of claim 8 , further comprising:
logic coupled to an output of the FIFO and configured to generate a pulse; and
a multiplexer configured to pass data received from the memory array if the pulse is de-asserted, and to prevent the data from passing if the pulse is asserted.

10. A method of operating a memory interface circuit, comprising:
selectively operating the memory interface in either a synchronous mode or an asynchronous mode;
in the synchronous mode, controlling an address register for registering an address of a memory location in a memory array, the address register controlled by a first clock signal and not by an asynchronous address control signal, wherein the first clock signal synchronized to a second clock signal that is faster than a third clock signal used to operate the memory array by a control signal logic; and
in the asynchronous mode, controlling an address latch for latching the address of the memory location in the memory array, the address latch controlled by the asynchronous address control signal, wherein the asynchronous address control signal synchronized to the second clock signal,
wherein the control signal logic further generates concurrently a separately applied signal to stabilize an output of the memory array.

11. The method of claim 10 , further comprising:
selectively outputting the contents of the address latch or the contents of the address register, depending on the operating mode.

12. The method of claim 10 , further comprising:
controlling a data latch that receives data from the memory array in the asynchronous mode, using an asynchronous data control signal synchronized to the second clock signal.

13. The method of claim 12 , further comprising:
synchronizing the asynchronous data control signal to the second clock signal using a one-shot circuit.

14. The method of claim 12 , further comprising:
operating the data latch to open as early as possible to accept data output from the memory location, and operating the data latch to close in sync with the second clock signal.

15. The method of claim 10 , further comprising:
accessing the memory array in the synchronous mode during a first time period and accessing the memory array in the asynchronous mode during a second time period, the second time period being distinct from the first time period.

16. The method of claim 10 , further comprising:
accessing in the synchronous mode a first memory array of a plurality of memory arrays; and
accessing in the asynchronous mode a second memory array of the plurality of memory arrays.

17. The method of claim 10 , further comprising:
propagating the first clock signal or the asynchronous address control signal along a FIFO chain in synchronization with the second clock signal.

18. The method of claim 17 , further comprising:
generating an output pulse from the FIFO chain;
receiving data from the memory array if the pulse is de-asserted; and
preventing the data from being received by the memory interface if the pulse is asserted.

Assignees

• Khodabandehlou Hamid
• Raza Syed Babar
• Cypress Semiconductor Corp

Inventors

• Khodabandehlou Hamid
• Raza Syed Babar

Classifications

• B21C23/085 Primary

  Making tubes (B21C23/10 take precedence) · CPC title

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title