Display power saving utilizing non volatile memory

Patent metadata

Field	Value
Publication number	US-9734775-B2
Application number	US-201414179708-A
Country	US
Kind code	B2
Filing date	Feb 13, 2014
Priority date	Feb 13, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A device includes a controller configured to receive information for display, an LCD display coupled to the controller, the LCD display comprising an array of pixel elements, and a non-volatile random access memory (NVRAM) coupled to the controller and to the LCD display to receive data for each pixel element and provide that data to the pixel elements for display.

First claim

The invention claimed is:

1. A display device comprising:
a controller to couple to a graphics adapter external to the display device to receive information for display by the display device;
an LCD display coupled to the controller, the LCD display comprising an array of pixel elements; and
a non-volatile random access memory (NVRAM) coupled to the controller and to the LCD display to receive data from the controller for each pixel element and provide that data to the pixel elements for display, wherein the NVRAM comprises memory cells embedded in each pixel element, such embedded memory cells coupled to provide pixel data to the pixel element with which it is embedded; wherein the display device is operable to self-refresh to enable the graphics adapter to enter a reduced power consumption state during continued display of the last information provided by the graphics adapter.

2. The device of claim 1 wherein the non-volatile memory comprises magnetic random access memory (MRAM), and wherein the information for display is received from a graphics adapter, and wherein the MRAM refreshes the array of pixel elements under control of the controller.

3. The device of claim 1 wherein the non-volatile memory comprises spin torque transfer random access memory (STT-RAM).

4. The device of claim 3 wherein the STT-RAM comprises an array of memory cells embedded with each memory cell corresponding to a pixel element.

5. The device of claim 4 wherein each memory cell is positioned beneath each pixel element.

6. The device of claim 1 wherein the controller is to place the memory and array of pixel elements into a self-refresh mode.

7. The device of claim 6 wherein the controller is further operable to place itself in a lower power consumption mode following placing the memory and array of pixel elements into the self-refresh mode.

8. The device of claim 1 and further comprising a backlight coupled to illuminate the array of pixel elements.

9. A device comprising:
a controller to receive information for display;
an LCD display coupled to the controller, the LCD display comprising an array of pixel elements;
a non-volatile random access memory (NVRAM) coupled to the controller and to the LCD display to receive data for each pixel element from the controller and provide that data to the pixel elements for display, wherein the NVRAM comprises memory cells embedded in each pixel element, such embedded memory cells coupled to provide pixel data to the pixel element with which it is embedded;
processing circuitry;
a random access memory coupled to the processing circuitry; and
graphics processing circuitry coupled to the processing circuitry to provide the information to display to the controller; wherein the controller is operable to place the memory and array of pixel elements into a self-refresh mode, and wherein the controller is further operable to place itself in a lower power consumption mode following placing the memory and array of pixel elements into the self-refresh mode.

10. The device of claim 9 wherein the processing circuitry and the graphics processing circuitry are operable to enter a low power mode and to provide a self-refresh command to the controller.

11. The device of claim 9 wherein the non-volatile memory comprises spin torque transfer random access memory (STT-RAM).

12. The device of claim 11 wherein the SIT-RAM comprises an array of memory cells, each memory cell corresponding to a pixel element.

13. A method comprising:
receiving a self-refresh command at a controller of a liquid crystal display (LCD) device;
placing a non-volatile random access memory (NVRAM) in a self-refresh mode to cause the NVRAM to provide pixel data received from the controller to an array of pixel elements of the LCD to refresh the pixel elements, wherein the NVRAM comprises memory cells embedded in each pixel element, such embedded memory cells coupled to provide pixel data to the pixel element with which it is embedded;
continuously displaying the pixel data via the pixel elements; and
placing the controller in a low power consumption mode following placing the NVRAM in the self-refresh mode.

14. The method of claim 13 and further comprising placing graphics processing circuitry from which the self-refresh command was received by the controller in a low power consumption mode following issuance of the self-refresh command.

15. The method of claim 14 and further comprising placing processing circuitry coupled to the graphics processing circuitry into a low power consumption mode.

16. A system comprising:
a processor;
a graphics adapter coupled to the processor; and
a display device coupled to receive display information from the graphics adapter, the display comprising:
a controller to receive the display information;
a spin torque transfer random access memory (STT-RAM) coupled to the controller to receive pixel information from the controller based on the display information; and
an array of pixels coupled to the STT-RAM to display the pixel information, wherein the STT-RAM comprises memory cells embedded in each pixel, such embedded memory cells coupled to provide pixel data to the pixel with which it is embedded.

17. The system of claim 16 wherein the STT-RAM comprises an array of memory cells, each memory cell corresponding to a pixel element.

18. The system of claim 17 wherein each memory cell is positioned beneath each pixel element.

19. The system of claim 16 wherein the controller is operable to place the memory and array of pixel elements into a self-refresh mode.

20. The system of claim 19 wherein the controller is further operable to place itself in a lower power consumption mode following placing the memory and array of pixel elements into the self-refresh mode.

21. The system of claim 16 and further comprising a backlight coupled to illuminate the array of pixel elements.

Assignees

• Lenovo Singapore Pte Ltd

Inventors

• Davis Mark Charles
• Locker Howard J
• Kelso Scott Edwards
• Perrin Steven Richard

Classifications

• G09G3/3611 Primary

  Control of matrices with row and column drivers · CPC title

• G09G2300/0857

  Static memory circuit, e.g. flip-flop · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title