Software methods in a GPU

Patent metadata

Field	Value
Publication number	US-9734545-B2
Application number	US-90032910-A
Country	US
Kind code	B2
Filing date	Oct 7, 2010
Priority date	Oct 8, 2009
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

One embodiment of the present invention sets forth a technique for executing a software method within a graphics processing unit (GPU) that minimizes the number of clock cycles during which the graphics engine is idled. The function of the software method is performed by a firmware method that is executed by a processor within the GPU. The firmware method is executed to access and optionally update the state stored in the GPU. Unlike execution of a conventional software method, execution of the firmware method does not require an exchange of information between a CPU and the GPU. Therefore, the CPU is not interrupted and throughput of the CPU is not reduced.

First claim

We claim:

1. A method for executing software methods, comprising:
receiving, by a front end unit of a graphics processing unit (GPU), a firmware method that is configured to perform a function of a corresponding software method, wherein the firmware method is configured for execution only within the GPU, whereas the corresponding software method is configured for execution in conjunction with a central processing unit (CPU);
in response to receiving the firmware method, issuing, by the front end unit, an interrupt to a processor within the GPU that is configured to execute the firmware method, instead of issuing the interrupt to the CPU;
executing, by the processor, the firmware method; and
clearing the interrupt by the processor.

2. The method of claim 1 , wherein the executing of the firmware method comprises reading, by the processor, a first control register within a graphics processing pipeline of the GPU.

3. The method of claim 1 , wherein the executing of the firmware method comprises writing, by the processor, a first control register within a graphics processing pipeline of the GPU based on the firmware method.

4. The method of claim 3 , wherein the executing of the firmware method comprises waiting for the graphics processing pipeline to become idle prior to the writing of the first control register.

5. The method of claim 1 , wherein the executing of the firmware method comprises reading, by the processor, data for state methods sent by the front end unit to a graphics processing pipeline of the GPU.

6. The method of claim 5 , wherein the executing of the firmware method comprises writing, by the processor, at least a portion of the data for state methods sent by the front end unit to a graphics processing pipeline.

7. The method of claim 1 , further comprising storing input parameters for the firmware method in a portion of the front end unit that is accessible to the processor.

8. The method of claim 1 , wherein the executing of the firmware method comprises writing, by the processor, an output parameter to the front end unit.

9. The method of claim 1 , further comprising resuming processing of a command stream by the front end unit.

10. The method of claim 1 , further comprising:
determining that data for state methods sent by the front end unit to a graphics processing pipeline should be overridden;
waiting for the graphics processing pipeline to become idle;
changing the data for the state methods; and
after clearing the interrupt by the processor, resuming processing by the graphics processing pipeline using the changed data for the state methods.

11. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, execute a software method, by performing the steps of:
receiving, by a front end unit of a graphics processing unit (GPU), a firmware method that is configured to perform a function of a corresponding software method, wherein the firmware method is configured for execution only within the GPU, whereas the corresponding software method is configured for execution in conjunction with a central processing unit (CPU);
in response to receiving the firmware method, issuing, by the front end unit, an interrupt to a processor within the GPU that is configured to execute the firmware method, instead of issuing the interrupt to the CPU;
executing, by the processor, the firmware method; and
clearing the interrupt by the processor.

12. The non-transitory computer-readable storage medium of claim 11 , further comprising
resuming processing of a command stream by the front end unit.

13. The non-transitory computer-readable storage medium of claim 11 , further comprising:
determining that data for state methods sent by the front end unit to a graphics processing pipeline should be overridden;
waiting for the graphics processing pipeline to become idle;
changing the data for the state methods; and
after clearing the interrupt by the processor, resuming processing by the graphics processing pipeline using the changed data for the state methods.

14. The non-transitory computer-readable storage medium of claim 11 , further comprising:
receiving, by the front end unit, a plurality of method parameters related to the firmware method, wherein the plurality of method parameters are stored within the front end unit; and
reading, by the processor, the plurality of method parameters stored within the front end unit.

15. A system for executing software methods, the system comprising:
a graphics processing unit (GPU) that is coupled to a central processing unit (CPU), the GPU comprising:
a front end unit configured to
receive a firmware method that is configured to perform a function of a corresponding software method, wherein the firmware method is configured for execution only within the GPU, whereas the corresponding software method is configured for execution in conjunction with the CPU; and
in response to receiving the firmware method, issue an interrupt to a processor within the GPU, instead of issuing the interrupt to the CPU; and

the processor configured to execute the firmware method.

16. The system of claim 15 , wherein the GPU further comprises a graphics processing pipeline and the processor is configured to read a first control register within the graphics processing pipeline during execution of the firmware method.

17. The system of claim 15 , wherein the processor is configured to write a first control register within a graphics processing pipeline of the GPU based on the firmware method.

18. The system of claim 17 , wherein the processor is configured to wait for the graphics processing pipeline to become idle prior to the writing of the first control register.

19. The system of claim 15 , wherein the GPU further comprises a graphics processing pipeline and the processor is configured to read data for state methods sent by the front end unit to the graphics processing pipeline during execution of the firmware method.

20. The system of claim 15 , wherein the processor is further configured to clear the interrupt after execution of the firmware method and the front end unit is configured to resume processing of a command stream when the interrupt is cleared.

21. The system of claim 15 , wherein the processor is further configured to:
determine that data for state methods sent by the front end unit to a graphics processing pipeline should be overridden;
wait for the graphics processing pipeline to become idle;
change the data for the state methods; and
clear the interrupt to resume processing by the graphics processing pipeline using the changed data for the state methods.

Assignees

• Duluk Jr Jerome F
• Cook John Christopher
• Gruner Fred
• Palmer Gregory Scott
• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Cook John Christopher
• Gruner Fred
• Palmer Gregory Scott

Classifications

• G09G5/363

  Graphics controllers · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title