Data transfer control apparatus, data transfer control method, and computer product

Patent metadata

Field	Value
Publication number	US-9734104-B2
Application number	US-201514630235-A
Country	US
Kind code	B2
Filing date	Feb 24, 2015
Priority date	Jun 22, 2010
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

First claim

What is claimed is:

1. A data transfer control apparatus comprising:
a direct memory access controller configured to transfer data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and
the first processor configured to:
detect a process being executed by the first processor,
determine whether transfer of the data is urgent, based on the type of the detected process,
when the transfer is determined to be urgent, instruct the direct memory access controller to transfer the data, and
when the transfer is determined to not be urgent, read the data from the transfer source memory or the transfer destination memory.

2. A data transfer control method executed by a processor for controlling a direct memory access controller that transfers data from a transfer source memory to a transfer destination memory, the data transfer control method comprising:
detecting a process executed by the processor;
determining whether transfer of the data is urgent, based on the type of the detected process;
instructing the direct memory access controller to transfer the data, when the transfer is determined to be urgent; and
reading the data from the transfer source memory or the transfer destination memory by the processor when the transfer is determined to not be urgent.

3. A multi processor system comprising:
a plurality of cores,
a plurality of memories configured to store processed data processed by the plurality of cores, respectively, and
a direct memory access controller configured to conduct data transferring processes between the plurality of memories,
wherein, one of the plurality of cores
sets priority of the data transferring processes between the memories based on type of the processes processed by the plurality of cores,
instructs the direct memory access controller to transfer the data when the priority is high, and
reads the data from the plurality of memories when the priority is low.

4. A method for controlling a multi processor system that includes a plurality of cores, a plurality of memories configured to store processed data processed by the plurality of cores, respectively, and a direct memory access controller configured to conduct data transferring processes between the plurality of memories, the method comprising:
setting, by one of the plurality of cores, priority of data transferring processes between the plurality of memories based on type of the processes processed by the plurality of cores,
instructing the direct memory access controller to transfer the data when the priority is high, and
reading the data from the plurality of memories when the priority is low.

5. A data transfer control apparatus comprising:
a processor:
a direct memory access controller configured to transfer data from a transfer source memory to a transfer destination memory, according to an instruction from the processor; and
a data transfer table in which a type of a process is related to a data transfer scheme, the processor being configured to
detect a process being executed by the processor,
determine a data transfer scheme corresponding to the type of the detected process based on the data transfer table, and
control the direct memory access controller to transfer the data or read the data from the transfer source memory or the transfer destination memory, based on the data transfer scheme.

Assignees

• Fujitsu Ltd

Inventors

• Yamauchi Hiromasa
• Yamashita Sr Koichiro
• Suzuki Takahisa
• Kurihara Koji

Classifications

• G06F13/30

  with priority control · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title