Cache organization and method

Patent metadata

Field	Value
Publication number	US-9734080-B2
Application number	US-201313962429-A
Country	US
Kind code	B2
Filing date	Aug 8, 2013
Priority date	Aug 8, 2013
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata, which contains the tag, way, and line for a corresponding cache entry, along with a valid bit, allowing a memory access which hits a location in the cache to go directly to the cache's data array, avoiding the need to look up the address in the cache's tag array. When a cache line is evicted, any metadata referring to the line is marked as invalid. By reducing the number of tag lookups performed to access data in a cache's data array, the power that would otherwise be consumed by performing tag lookups is saved, thereby reducing power consumption of the information processing system, and the cache area needed to implement a cache having a desired level of performance may be reduced.

First claim

What is claimed is:

1. A method comprising:
associating a register, in a processor core, storing an operand address of an operand of an executing instruction with cache-oriented metadata indicating a location of the operand; and
invalidating the cache-oriented metadata in response to an invalid cache address for a cache in the processor core being written to the register.

2. The method of claim 1 further comprising:
in response to a cache line being evicted from a cache, invalidating second cache-oriented metadata.

3. The method of claim 1 further comprising:
in response to beginning execution of a data transfer instruction referring to a register, wherein cache-oriented metadata corresponding to the register is invalid, performing a cache tag lookup, performing a cache replacement, updating the cache-oriented metadata to reflect the cache replacement, and validating the cache-oriented metadata.

4. The method of claim 1 wherein the register is a program counter.

5. An information processing system comprising:
a register, in a processor core, storing an operand address of an operand of an executing instruction with which cache-oriented metadata is associated indicating a location of the operand; and
a cache-oriented metadata supervisory agent for invalidating the cache-oriented metadata in response to an invalid cache address for a cache in the processor core being written to the register.

6. The information processing system of claim 5 wherein a processor register subsystem comprises the register and processor register metadata storage, wherein the processor register metadata storage stores the cache-oriented metadata when the cache-oriented metadata is valid.

7. The information processing system of claim 5 wherein the cache-oriented metadata enables access to a cache line of a cache without performing a cache tag lookup operation when it is already known that a particular location of a data array of the cache has a tag that corresponds to an address of the register.

8. The information processing system of claim 5 wherein the cache-oriented metadata selects a cache line of a cache data array of the cache in response to the cache-oriented metadata being valid, and a cache tag array is used to select the cache line of the cache data array of the cache in response to the cache-oriented metadata being invalid.

9. The method of claim 1 further comprising:
associating a second register in a second processor core with second cache-oriented metadata; and
invalidating the second cache-oriented metadata in response to a second invalid cache address for a second cache in the second processor core being written to the second register.

10. The method of claim 1 wherein a processor register subsystem comprises the register and processor register metadata storage, wherein the processor register metadata storage stores the cache-oriented metadata.

11. The method of claim 10 wherein the processor register metadata storage stores the cache-oriented metadata when the cache-oriented metadata is valid.

12. The method of claim 1 wherein the cache-oriented metadata enables access to a cache line of a cache without performing a cache tag lookup operation when it is already known that a particular location of a data array of the cache has a tag that corresponds to an address of the register.

13. The method of claim 1 wherein the cache-oriented metadata selects a cache line of a cache data array of the cache in response to the cache-oriented metadata being valid, and a cache tag array is used to select the cache line of the cache data array of the cache in response to the cache-oriented metadata being invalid.

14. The information processing system of claim 5 further comprising:
a second register in a second processor core with which second cache-oriented metadata is associated; and
a second cache-oriented metadata supervisory agent for invalidating the second cache-oriented metadata in response to a second invalid cache address for a second cache in the second processor core being written to the second register.

15. The information processing system of claim 5 wherein the cache-oriented metadata comprises a pointer to a cache line in a cache data array of a cache.

16. The information processing system of claim 5 wherein the cache-oriented metadata enables access to a cache line of a cache without performing a cache tag lookup operation.

17. The information processing system of claim 5 wherein the cache-oriented metadata identifies a cache line for a corresponding cache entry of a cache.

18. The information processing system of claim 5 wherein the cache-oriented metadata comprises a validity indicator to indicate the validity of the cache-oriented metadata, wherein the cache-oriented metadata supervisory agent invalidates the cache-oriented metadata by changing a value of the validity indicator.

19. The information processing system of claim 5 wherein, in response to beginning execution of a data transfer instruction referring to a register, wherein cache-oriented metadata corresponding to the register is invalid, a cache tag lookup is performed, a cache replacement is performed, the cache-oriented metadata supervisory agent updates the cache-oriented metadata to reflect the cache replacement, and the cache-oriented metadata supervisory agent validates the cache-oriented metadata.

20. The information processing system of claim 5 wherein the register is a program counter.

Assignees

• Wilson Peter J
• Nxp Usa Inc

Inventors

• Wilson Peter J

Classifications

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title