Cache structure and management method for use in implementing reconfigurable system configuration information storage

Patent metadata

Field	Value
Publication number	US-9734056-B2
Application number	US-201314425456-A
Country	US
Kind code	B2
Filing date	Nov 13, 2013
Priority date	Dec 13, 2012
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A cache structure for use in implementing reconfigurable system configuration information storage, comprises: layered configuration information cache units: for use in caching configuration information that may be used by a certain or several reconfigurable arrays within a period of time; an off-chip memory interface module: for use in establishing communication; a configuration management unit: for use in managing a reconfiguration process of the reconfigurable arrays, in mapping each subtask in an algorithm application to a certain reconfigurable array, thus the reconfigurable array will, on the basis of the mapped subtask, load the corresponding configuration information to complete a function reconfiguration for the reconfigurable array. This increases the utilization efficiency of configuration information caches. Also provided is a method for managing the reconfigurable system configuration information caches, employing a mixed priority cache update method, and changing a mode for managing the configuration information caches in a conventional reconfigurable system, thus increasing the dynamic reconfiguration efficiency in a complex reconfigurable system.

First claim

The invention claimed is:

1. A cache structure for implementing reconfigurable system configuration information storage, comprising hierarchical configuration information cache units memories, an off-chip memory interface, and a configuration management unit processor:
the hierarchical configuration information cache memories are configured to cache configuration information that may be used by one or more reconfigurable arrays within a time period; the off-chip memory interface module is configured to establish communication between the hierarchical configuration information cache memories and external memory;
the configuration management processor is configured to manage a reconfiguration process of the reconfigurable arrays, comprising: map subtasks in an algorithm application to a reconfigurable array, and set a prioritizing strategy for the hierarchical configuration information cache memories: when a new subtask is mapped to a reconfigurable array, the reconfigurable array will load the corresponding configuration information according to the mapped subtask, and accomplish functional reconfiguration of the reconfigurable array.

2. The cache structure for implementing reconfigurable system configuration information storage according to claim 1 , wherein, the hierarchical configuration information cache memories comprise L1 configuration information caches, L2 configuration information caches, and a L3 configuration information cache;
the L1 configuration information cache is closely coupled to a single reconfigurable array, and is configured to cache the configuration information that may be used only by the reconfigurable array within a time period;
the L2 configuration information cache is closely coupled to a single reconfigurable processing unit, and is configured to cache the configuration information that may be used by multiple reconfigurable arrays in the same reconfigurable processing unit within a time period;
the L3 configuration information cache can be accessed by multiple reconfigurable processing units in a shared mode, and is configured to cache the configuration information that may be used by the reconfigurable arrays in multiple reconfigurable processing units within a time period.

3. A configuration information cache management method that utilizes the cache structure for implementing reconfigurable system configuration information storage as set forth in claim 2 , wherein, the method classifies the configuration information into three priority levels, and employs a mixed priority management strategy based on the three-level prioritization mechanism; the three priority levels comprise: frequency priority, which reflects whether a set of configuration information is read frequently; correlation priority, which reflects whether there is an invocation relationship among different sets of configuration information; computation complexity priority, which reflects whether a set of configuration information has to be accomplished by multiple reconfigurable arrays; the mixed priority management strategy is as follows: (1) for a set of configuration information with high frequency priority and low computation complexity priority, keep the set of configuration information in the L1 configuration information caches preferentially; (2) for a set of configuration information with high frequency priority and high computation complexity priority, judge whether the reconfigurable arrays that require a current set of configuration information are in the same reconfigurable processing unit; if these reconfigurable arrays are in the same reconfigurable processing unit, keep the current set of configuration information in the L2 configuration information caches preferentially; otherwise, keep the current set of configuration information in the L2 configuration information caches and the L3 configuration information cache preferentially; (3) if the current set of configuration information has high priority of correlation with several other sets of configuration information, set those sets of configuration information as preferential replacement candidates once the current set of configuration information is replaced out of the configuration information cache memories.

4. The cache structure for implementing reconfigurable system configuration information storage according to claim 1 , wherein, the configuration management processor further sets a prioritizing strategy for the hierarchical configuration information cache memories.

5. The cache structure for implementing reconfigurable system configuration information storage according to claim 1 , wherein, a hierarchical configuration information cache memory comprises:
a configuration information memory, which is configured to store the configuration information of the reconfigurable arrays temporarily;
a configuration information priority look-up table, which is configured to store priority setting information of configuration information;
a configuration cache control logic unit, which is configured to manage read access to the configuration information memory and an update of configuration information in the configuration information memory;
a configuration information input interface, which is configured to receive externally inputted configuration information, so that the configuration cache control logic unit can store the received externally inputted configuration information into the configuration information memory;
a configuration information output interface, which is configured to enable external modules to read the configuration information in the configuration information memory.

6. The cache structure for implementing reconfigurable system configuration information storage according to claim 5 , wherein, the configuration information cache memory further comprises: a priority setting interface, configured to initialize a priority setting in the configuration information cache memory, and input the priority setting information into the configuration information priority look-up table.

Assignees

• Univ Southeast

Inventors

• Shi Longxing
• Yang Jun
• Cao Peng
• Liu Bo
• Yang Jinjiang
• Liu Leibo
• Yin Shouyi
• Wei Shaojun

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F2212/601

  Reconfiguration of cache memory · CPC title

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title