Mapping of guest instruction block assembled according to branch prediction to translated native conversion block

Patent metadata

Field	Value
Publication number	US-9733942-B2
Application number	US-201213360024-A
Country	US
Kind code	B2
Filing date	Jan 27, 2012
Priority date	Jan 27, 2011
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.

First claim

What is claimed is:

1. A hardware based translation accelerator, comprising:
a guest fetch logic component for accessing a plurality of guest instructions;
a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling the plurality of guest instructions into a guest instruction block based on branch predictions;
a plurality of conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block;
a native cache coupled to the conversion tables for storing the corresponding native conversion block;
a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block;
wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache; and
in response to the hit the conversion look aside buffer forwards the translated native instruction for execution.

2. The hardware based translation accelerator of claim 1 , wherein a hardware fetch logic component prefetches the plurality of guest instructions independent of the processor.

3. The hardware based translation accelerator of claim 1 , wherein the conversion look aside buffer comprises a cache that uses a replacement policy to maintain most frequently encountered native conversion blocks stored therein.

4. The hardware based translation accelerator of claim 1 , wherein a conversion buffer is maintained within a system memory and cache coherency is maintained between the conversion look aside buffer and the conversion buffer.

5. The hardware based translation accelerator of claim 4 , wherein the conversion buffer is larger than the conversion look aside buffer, and a write back policy is used to maintain coherency between the conversion buffer and the conversion look aside buffer.

6. The hardware based translation accelerator of claim 1 , wherein the conversion look aside buffer is implemented as a high-speed low latency cache memory coupled to a pipeline of the processor.

7. A system for accelerating the translation of guest instructions to native instructions for a processor, comprising:
a guest fetch logic component for accessing a plurality of guest instructions;
a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling the plurality of guest instructions into a guest instruction block based on branch predictions;
a plurality of conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block;
a native cache coupled to the conversion tables for storing the corresponding native conversion block;
a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block;
wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache; and
in response to the hit the conversion look aside buffer forwards the translated native instruction for execution.

8. The system of claim 7 , wherein a hardware fetch logic component prefetches the plurality of guest instructions independent of the processor.

9. The system of claim 7 , wherein the conversion look aside buffer comprises a cache that uses a replacement policy to maintain most frequently encountered native conversion blocks stored therein.

10. The system of claim 7 , wherein a conversion buffer is maintained within a system memory and cache coherency is maintained between the conversion look aside buffer and the conversion buffer.

11. The system of claim 10 , wherein the conversion buffer is larger than the conversion look aside buffer, and a write back policy is used to maintain coherency between the conversion buffer and the conversion look aside buffer.

12. The system of claim 7 , wherein the conversion look aside buffer is implemented as a high-speed low latency cache memory coupled to a pipeline of the processor.

13. A microprocessor that implements a method of translating instructions, said microprocessor comprises:
a microprocessor pipeline;
a hardware accelerator module coupled to the microprocessor pipeline, wherein the hardware accelerator module further comprises:
a guest fetch logic component for accessing a plurality of guest instructions;
a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling the plurality of guest instructions into a guest instruction block based on branch predictions;
a plurality of conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block;
a native cache coupled to the conversion tables for storing the corresponding native conversion block;
a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block;
wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache; and
in response to the hit the conversion look aside buffer forwards the translated native instruction for execution.

14. The microprocessor of claim 13 , wherein a hardware fetch logic component prefetches the plurality of guest instructions independent of the processor.

15. The microprocessor of claim 13 , wherein the conversion look aside buffer comprises a cache that uses a replacement policy to maintain most frequently encountered native conversion blocks stored therein.

16. The microprocessor of claim 13 , wherein a conversion buffer is maintained within a system memory and cache coherency is maintained between the conversion look aside buffer and the conversion buffer.

17. The microprocessor of claim 16 , wherein the conversion buffer is larger than the conversion look aside buffer, and a write back policy is used to maintain coherency between the conversion buffer and the conversion look aside buffer.

18. The microprocessor of claim 13 , wherein the conversion look aside buffer is implemented as a high-speed low latency cache memory coupled to a pipeline of the processor.

19. The microprocessor of claim 13 , wherein the hardware accelerator module functions comprises a parallel guest instruction fetch pipeline that functions in parallel to a native microprocessor fetch pipeline.

20. A microprocessor that implements a method of translating instructions, said microprocessor comprises:
a microprocessor pipeline;
an accelerator module comprising high speed memory coupled to the microprocessor pipeline, wherein the accelerator module further comprises:
a guest fetch logic for accessing a plurality of guest instructions;
a guest fetch memory coupled to the guest fetch logic and a branch prediction component for assembling the plurality of guest instructions into a guest instruction block based on branch predictions;
a plurality of conversion tables for translating the guest instruction blo

Assignees

• Abdallah Mohammad
• Intel Corp

Inventors

• Abdallah Mohammad

Classifications

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G06F9/3814

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/3879

  for non-native instruction execution, e.g. executing a command; for Java instruction set · CPC title

• G06F9/45516

  Runtime code conversion or optimisation · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title