Memory system including nonvolatile memory device and erase method thereof

Patent metadata

Field	Value
Publication number	US-9733864-B2
Application number	US-201414527092-A
Country	US
Kind code	B2
Filing date	Oct 29, 2014
Priority date	Jan 21, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

An erase method of a nonvolatile memory device is provided which includes receiving an erase request; selecting an erase mode of a memory block corresponding to the erase request, based on an access condition of the nonvolatile memory device managed by a memory controller; and controlling the nonvolatile memory device to erase the memory block according to the selected erase mode. The erase mode includes a fast erase mode of which an erase time for the memory block is shorter than a reference time and a slow erase mode of which an erase time for the memory block is longer than the reference time.

First claim

What is claimed is:

1. An erase method of a nonvolatile memory device comprising:
receiving an erase request;
selecting an erase mode among a plurality of erase modes of a memory block corresponding to the erase request, based on an access condition of the nonvolatile memory device managed by a memory controller, the access condition including a status of a write buffer in which data to be written to the nonvolatile memory device is temporarily stored; and
controlling the nonvolatile memory device to erase the memory block according to the selected erase mode,
wherein the plurality of erase modes include a fast erase mode of which an erase time for the memory block is shorter than a reference time and a slow erase mode of which an erase time for the memory block is longer than the reference time.

2. The erase method of claim 1 , wherein a level of an erase start pulse provided at the slow erase mode is lower than a level of an erase start pulse provided at the fast erase mode.

3. The erase method of claim 2 , wherein the level of the erase start pulse provided at the slow erase mode gradually increases from a first voltage to a second voltage.

4. The erase method of claim 2 , wherein a width of the erase start pulse provided at the slow erase mode is wider than a width of the erase start pulse provided at the fast erase mode.

5. The erase method of claim 1 , wherein the erase mode is selected based on a ratio of an empty area to a whole memory area of the write buffer.

6. The erase method of claim 1 , wherein the erase mode is selected based on a result of predicting an amount of data of the write buffer increased upon execution of the slow erase mode.

7. A storage device comprising:
a nonvolatile memory device including a plurality of memory blocks and configured to erase a selected memory block according to an erase mode among a plurality of erase modes with different erase times; and
a memory controller including a write buffer and configured to determine an erase mode of the selected memory block with reference to a status of the write buffer,
wherein the plurality of erase modes comprises a fast erase mode of which an erase time is shorter than a reference time and a slow erase mode of which the erase time is longer than the reference time.

8. The storage device of claim 7 , wherein the memory controller determines the erase mode to prevent the write buffer from overflowing.

9. The storage device of claim 7 , wherein the memory controller determines the erase mode based on a result of predicting an amount of data of the write buffer increased upon execution of the plurality of erase modes.

10. The storage device of claim 7 , wherein a voltage level of an erase start pulse applied to the selected memory block in the slow erase mode is lower than a voltage level of an erase start pulse applied to the selected memory block in the fast erase mode.

11. The storage device of claim 10 , wherein a pulse width of the erase start pulse applied to the selected memory block in the slow erase mode is wider than a pulse width of the erase start pulse applied to the selected memory block in the fast erase mode.

12. The storage device of claim 7 , wherein a voltage level of an erase start pulse applied to the selected memory block in the slow erase mode is incrementally increased during a period of the erase start pulse.

Assignees

• Moon Sangkwon
• Kim Jihong
• Jeong Jaeyong
• Kim Kyung Ho
• Samsung Electronics Co Ltd
• Snu R&Db Foundation

Inventors

• Moon Sangkwon
• Kim Jihong
• Jeong Jaeyong
• Kim Kyung Ho

Classifications

• G06F3/0652 Primary

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/72

  Details relating to flash memory management · CPC title