Interlock detector with self-diagnosis function for an interlock circuit, and method for the self-diagnosis of the interlock detector

Patent metadata

Field	Value
Publication number	US-9733303-B2
Application number	US-201314388803-A
Country	US
Kind code	B2
Filing date	Mar 11, 2013
Priority date	Mar 28, 2012
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

The interlock detector includes a first input, wherein a first output signal from an interlock generator is applied to the first input. The interlock detector further includes a second output which is configured to provide a microprocessor with a second output signal. The interlock detector further includes a differential amplifier that includes a second input, a third input, and a third output, wherein the second input and the third input are connected to the first input. The interlock detector further includes a comparator circuit that includes a fourth input and a fourth output, wherein the fourth input is connected to the third output, the fourth output is connected to the second output, and the fourth input is positioned between the comparator circuit and the differential amplifier.

First claim

The invention claimed is:

1. An interlock detector comprising:
a first differential input of the interlock detector configured to connect to a signal loop of an interlock circuit to receive a first signal from an interlock generator arranged in the signal loop of the interlock circuit;
an output of the interlock detector configured to connect to a microprocessor and provide the microprocessor with a second signal;
a differential amplifier circuit having at least one amplifier, the differential amplifier circuit having a first input, a second input, and an output, the first input of the differential amplifier circuit and the second input of the differential amplifier circuit being connected to the first differential input of the interlock detector;
a comparator circuit having at least one comparator, the comparator circuit having an input and an output, the input of the comparator circuit being connected to the output of the differential amplifier circuit, the output of the comparator circuit being connected to the output of the interlock detector;
at least one second input of the interlock detector configured to receive at least one a diagnosis signal, the at least one second input of the interlock detector being connected at least one of (i) the input of the comparator circuit, (ii) the first input of the differential amplifier circuit, and (iii) the second input of the differential amplifier circuit.

2. The interlock detector as claimed in claim 1 , wherein:
the at least one second input of the interlock detector is a plurality of second inputs of the interlock detector;
a first of the plurality of second inputs of the interlock detector is connected to the first input of the differential amplifier circuit;
a second of the plurality of second inputs of the interlock detector is connected to the second input of the differential amplifier circuit;
a third of the plurality of second inputs of the interlock detector is connected to the input of the comparator circuit; and
a fourth of the plurality of second inputs of the interlock detector is connected to the first differential input of the interlock detector.

3. The interlock detector as claimed in claim 1 , further comprising:
a switch connected between the output of the differential amplifier circuit and the input of the comparator circuit, the switch being configured to interrupt a connection between the output of the differential amplifier circuit and the input of the comparator circuit to diagnose the comparator circuit.

4. The interlock detector as claimed in claim 3 , wherein:
the at least one second input is connected to the input of the comparator circuit and configured to provide the diagnosis signal to the input of the comparator circuit; and
the switch is connected upstream of the connection between the at least one second input and the input of the comparator circuit.

5. The interlock detector as claimed in claim 1 , further comprising:
a switch connected between the at least one second input of the interlock detector and the at least one of (i) the input of the comparator circuit, (ii) the first input of the differential amplifier circuit, and (iii) the second input of the differential amplifier circuit.

6. An interlock detector system comprising:
an interlock circuit having a signal loop and an interlock generator arranged in the signal loop, the interlock generator being configured to generate a first signal in the signal loop;
a microprocessor; and
an interlock detector, the interlock detector comprising:
a first differential input of the interlock detector configured to connect to the signal loop of the interlock circuit to receive the a first signal from the interlock generator of the interlock circuit;
an output of the interlock detector configured to connect to the microprocessor and provide the microprocessor with a second signal;
a differential amplifier circuit having at least one amplifier, the differential amplifier circuit having a first input, a second input, and an output, the first input of the differential amplifier circuit and the second input of the differential amplifier circuit being connected to the first differential input of the interlock detector;
a comparator circuit having at least one comparator, the comparator circuit having an input and an output, the input of the comparator circuit being connected to the output of the differential amplifier circuit, the output of the comparator circuit being connected to the output of the interlock detector;
at least one second input of the interlock detector configured to receive at least one a diagnosis signal, the at least one second input of the interlock detector being connected at least one of (i) the input of the comparator circuit, (ii) the first input of the differential amplifier circuit, and (iii) the second input of the differential amplifier circuit,

wherein the microprocessor is connected to the at least one second input of the interlock detector and configured to (i) provide the diagnosis signal to the at least one second input of the interlock detector and (ii) evaluate the second signal provided by the output of the interlock detector.

7. The interlock detector system as claimed in claim 6 , wherein the microprocessor is configured to generate the diagnosis signals for the interlock detector via pulse width modulation signals and a respective low-pass filter between the microprocessor and the at least one second input of the interlock detector.

8. The interlock detector system as claimed in claim 6 , further comprising at least one switch arranged in the signal loop of the interlock circuit between the first differential input of the interlock detector and the interlock generator of the interlock circuit.

9. The interlock detector as claimed in claim 1 , wherein the interlock detector is comprised by a battery.

10. The interlock detector as claimed in claim 9 , wherein the battery is comprised by a motor vehicle.

Assignees

• Bosch Gmbh Robert
• Samsung Sdi Co Ltd

Inventors

• Schaedlich Thomas

Classifications

• B60L3/0046

  relating to electric energy storage systems, e.g. batteries or capacitors · CPC title

• G01R31/2834

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G01R31/2827

  Testing of electronic protection circuits (testing switches G01R31/327; checking alarm systems G08B29/00; self test of summation current transformers H02H3/335) · CPC title

• B60L3/12

  Recording operating variables {; Monitoring of operating variables} · CPC title

• B60L3/04

  Cutting off the power supply under fault conditions (protective devices and circuit arrangements in general H01H; H02H) · CPC title