Current detection circuit

Patent metadata

Field	Value
Publication number	US-9733284-B2
Application number	US-201615090810-A
Country	US
Kind code	B2
Filing date	Apr 5, 2016
Priority date	Apr 20, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

To provide a current detection circuit capable of suppressing the occurrence of a large potential difference between input terminals of a differential amplifier circuit, and preventing degradation of input transistors. A differential amplifier circuit is equipped with a clamp circuit which limits gate-source voltages of a pair of PMOS transistors each having a bulk and a source connected to each other with the sources of the pair of PMOS transistors as input terminals.

First claim

What is claimed is:

1. A current detection circuit comprising:
a differential amplifier circuit which adjusts a gate voltage of a first PMOS transistor according to a voltage generated by an input load current flowing across a first resistor, wherein the first PMOS transistor generates a detection current which is used to adjust an output transistor to thereby control the input load current, and the first resistor is connected in series with the output transistor, said generated detection current is used to monitor a value of the input load current,
wherein the differential amplifier circuit includes a clamp circuit for limiting gate-source voltages of a pair of PMOS transistors within the differential amplifier circuit, and each of the pair of PMOS transistors having a bulk and a source connected to each other, with the sources of each of the pair of PMOS transistors as input terminals to the differential amplifier circuit.

2. The current detection circuit according to claim 1 , wherein the clamp circuit comprises a series circuit of at least one MOS transistor having a gate and a drain connected to each other, and a resistive element, and
wherein the clamp circuit limits the gate-source voltages of the pair of PMOS transistors by using a gate-source voltage of the MOS transistor in which a drain current is limited by a parasitic diode between a drain and a bulk of the MOS transistor and the resistive element.

3. The current detection circuit according to claim 1 , wherein the clamp circuit comprises two MOS transistors each having a gate, a source and a bulk connected to each other and being connected in parallel in an opposite direction to each other, and wherein the clamp circuit limits the gate-source voltages of the pair of PMOS transistors by using parasitic diodes of the two MOS transistors.

Assignees

• Sii Semiconductor Corp

Inventors

• Igarashi Atsushi
• Otsuka Nao
• Sugiura Masakazu

Classifications

• H03F2200/91

  the amplifier has a current mode topology · CPC title

• G01R19/0023

  Measuring currents or voltages from sources with high internal resistance by means of measuring circuits with high input impedance, e.g. OP-amplifiers (electrostatic instruments G01R5/28; measuring electrostatic potential G01R15/165; measuring electrostatic fields G01R29/12; amplifiers per se H03F) · CPC title

• G01R19/0092 Primary

  Measuring current only · CPC title

• H03F3/45273

  Mirror types · CPC title

• H03K5/08

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title