Image sensor pixel with memory node having buried channel and diode portions

Patent metadata

Field	Value
Publication number	US-9729810-B2
Application number	US-201514665803-A
Country	US
Kind code	B2
Filing date	Mar 23, 2015
Priority date	Mar 23, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.

First claim

The invention claimed is:

1. An image sensor including a plurality of pixels disposed on a substrate, wherein each pixel comprises:
a photodiode disposed in a first region of the substrate;
a memory node disposed in a second region of the substrate, the second region being spaced from the first region;
a first transfer gate connected between the memory node and the photodiode;
a floating diffusion disposed in a third region of the substrate, the third region being spaced from the first and second regions; and
a second transfer gate connected between the memory node and the floating diffusion,
wherein the memory node includes a first buried channel portion disposed under the first transfer gate and having a first doping level, and a first diode portion and having a second doping level that is greater than the first doping level such that an intrinsic lateral electrical field is generated that drives electrons from the first buried channel portion into the first diode portion, and
wherein the floating diffusion of each said pixel further comprises a second buried channel portion disposed under the second transfer gate and having a third doping level, and a second diode portion having a fourth doping level that is greater than the third doping level such that a second intrinsic lateral electrical field is generated that drives electrons from the second buried channel portion into the second diode portion.

2. The image sensor of claim 1 ,
wherein the first buried channel portion and the first diode portion comprise n-type dopants, and
wherein each pixel further comprises:
a first p-type diffusion disposed under the first buried channel portion and the first diode portion of the memory node, and
a second p-type diffusion disposed between the first buried channel portion and the first diode portion of the memory node and an upper surface of the substrate.

3. The image sensor of claim 2 ,
wherein the first and second buried channel portions comprise a first n-type dopant such that the first doping level is equal to the third doping level,
wherein the first of the memory node comprises a combination of the first n-type dopant and a second n-type dopant, and
wherein the floating diffusion comprises a third n-type dopant configured such that the fourth doping level is greater than the second doping level.

4. The image sensor of claim 2 , wherein each pixel further comprises a light shield disposed over the floating diffusion, the second transfer gate, the memory node, and at least a portion of the first transfer gate.

5. The image sensor according to claim 2 ,
wherein the image sensor comprises a global shutter image sensor, and
wherein each said pixel further comprises:
a reset transistor connected between a voltage source and said floating diffusion and having a gate terminal operably coupled to receive a reset control signal;
a global reset transistor connected between said voltage source and said photodiode and having a gate terminal operably coupled to receive a global reset signal;
a source-follower transistor having a gate terminal connected to said floating diffusion; and
a row-select transistor connected between said source-follower transistor and a readout signal line, a gate terminal of said row-select transistor being connected to receive a row select control signal.

6. The image sensor according to claim 5 ,
wherein the plurality of pixels are disposed in an array including a plurality of rows and a plurality of columns, and
wherein the global shutter image sensor further comprises a control circuit including:
a first circuit portion configured to transmit a global reset control signal to the global reset transistor in all of the plurality of pixels such that a charge stored on the photodiode of all of the pixels of the pixel array is simultaneously reset to an initial photodiode charge at the beginning of a global shutter image capture operation, and such that the photodiode of each said pixel is controlled to generate a captured charge in accordance with an amount of light received by said each pixel during a first phase of the global shutter image capture operation;
a second circuit portion configured to transmit a first transfer gate control signal to the first transfer gate transistor in all of the plurality of pixels such that, in each said pixel, said captured charge is transferred from said photodiode to said memory node during a second phase of the global shutter image capture operation;
a third circuit portion configured to transmit sample-and-hold reset (SHR) control signals and sample-and-hold (SHS) control signals to said plurality pixels and to read out image data from said plurality of pixels during a rolling shutter readout operation such that only the pixels of a selected row of pixels receive said SHR control signals and said SHS control signals during a corresponding row-select time period of said rolling shutter readout operation,
wherein the third circuit portion is configured such that each said pixel of said selected row is controlled such that said floating diffusion of each said pixel stores a reset charge having a first voltage level, and said first voltage level is transmitted onto an associated column line in response to said SHR control signals during a first phase of said corresponding row-select time period, and
wherein the third circuit portion is configured such that each said pixel of said selected row is controlled such that said captured charge is transferred from said memory node to said floating diffusion of each said pixel, and a second voltage level generated by said captured charge is transmitted onto said associated column line in response to said SHS control signals during a second phase of said corresponding row-select time period.

7. The image sensor according to claim 6 ,
wherein the photodiode and the first diode portion of the memory node comprise pinned diode structures, and
wherein the second circuit portion is further configured such that said first transfer gate control signal transmitted to the first transfer gate transistor in all of the plurality of pixels has only two voltage levels.

8. The image sensor according to claim 5 ,
wherein the photodiode of each said pixel comprises a diode portion having a first doping profile configured to generate a first maximum charge potential, and
wherein said first diode portion has a second doping profile configured to generate a second maximum charge potential that is greater than the first maximum charge potential.

9. The image sensor according to claim 8 , wherein said floating diffusion of each said pixel comprises a third diode portion having a third doping profile configured to generate a third maximum charge potential that is greater than the second maximum charge potential.

10. A global shutter image sensor including a plurality of pixels disposed on a substrate, wherein each pixel comprises:
a photodiode disposed in a first region of the substrate;
a memory node disposed in a second region of the substrate, the second region being spaced from the first region;
a floating diffusion disposed in a third region of the substrate, the third region being spaced from the first and second regions;
a first transfer gate connected between the memory node and the photodiode; and
a second transfer gate connected between the memory node and the floating diffusion,
wherein the memory node includes a first buried channel portion disposed under the first transfer gate and having a first doping level, and a first diode portion and having a second doping level that is greater than the first doping level,
wherein the first diode portion of the memory node is configured to have a first

Assignees

• Tower Semiconductor Ltd

Inventors

• Lahav Assaf
• Fenigstein Amos
• Roizin Yakov
• Strum Avi

Classifications

• H04N25/771 Primary

  comprising storage means other than floating diffusion · CPC title

• H04N5/37452 Primary

  Electricity · mapped topic

• H01L27/14643

  Electricity · mapped topic

• H01L27/1461

  Electricity · mapped topic

• H01L27/14623

  Electricity · mapped topic