DARC signal demodulation circuit arrangement and method for operating same

Patent metadata

Field	Value
Publication number	US-9729365-B2
Application number	US-201515123057-A
Country	US
Kind code	B2
Filing date	Feb 2, 2015
Priority date	Mar 6, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A DARC signal demodulation circuit assemblage for recovering a DARC signal (DARC data) from an FM multiplex transmission signal includes: a pilot tone regulation circuit to obtain first and second mutually orthogonal oscillation synchronous with a stereo pilot tone encompassed by the FM multiplex transmission signal; a frequency quadruplication section for obtaining third and fourth mutually orthogonal oscillation having a frequency quadrupled as to the stereo pilot tone; a first multiplication section for obtaining a first multiplication signal from the FM multiplex transmission signal and from the third oscillation; a second multiplication section for obtaining a second multiplication signal from the FM multiplex transmission signal and from the fourth oscillation; first/second low-pass filters for obtaining first/second DARC signal components by low-pass filtration of the first and second multiplication signals; and an FM demodulation section for obtaining the DARC signal from a frequency demodulation of the first/second DARC signal components.

First claim

What is claimed is:

1. A Data Radio Channel (DARC) signal demodulation circuit assemblage for recovering a DARC signal, containing DARC data, from an FM multiplex transmission signal, comprising:
a pilot tone regulation circuit;
a frequency quadruplication circuit;
a multiplication component;
a low-pass filter; and
an FM demodulator;
wherein:
the pilot tone regulation circuit is configured to obtain a first oscillation and a second oscillation that are orthogonal to each other and are synchronous with a stereo pilot tone encompassed by the FM multiplex transmission signal;
the frequency quadruplication circuit is operatively coupled to the pilot tone regulation circuit to receive the first and second oscillations and is configured to obtain, based on the received first and second oscillations, a third oscillation and a fourth oscillation that are orthogonal to each other and have a frequency quadrupled with respect to the stereo pilot tone;
the multiplication component is operatively coupled to the frequency quadruplication circuit to receive the third oscillation and the fourth oscillation from the frequency quadruplication circuit, and the multiplication component is configured to obtain a first multiplication signal from the FM multiplex transmission signal and from the third oscillation received from the frequency quadruplication circuit and obtain a second multiplication signal from the FM multiplex transmission signal and from the fourth oscillation received from the frequency quadruplication circuit;
the low-pass filter is operatively coupled to the multiplication component to receive the first and second multiplication signals from the multiplication component, and the low-pass filter is configured to obtain a first DARC signal component by low-pass filtration of the first multiplication signal received from the multiplication component and obtain a second DARC signal component by low-pass filtration of the second multiplication signal received from the multiplication component; and
the FM demodulator is operatively coupled to the low-pass filter to receive the first and second DARC signal components and is configured to obtain the DARC signal from a frequency demodulation of the received first and second DARC signal components.

2. The DARC signal demodulation circuit assemblage of claim 1 , wherein the pilot tone regulation circuit is configured with a phase-locked loop to be latched onto the stereo pilot tone.

3. The DARC signal demodulation circuit assemblage of claim 1 , wherein the pilot tone regulation circuit is configured to derive, in a frequency- and phase-accurate manner with respect to the stereo pilot tone, a clock signal for obtaining the DARC data from the DARC signal.

4. The DARC signal demodulation circuit assemblage of claim 3 , further comprising a propagation time element that is downstream from the pilot tone regulation circuit and is configured to delay the clock signal derived by the pilot tone regulation circuit by an amount equal to a predefinable signal propagation time.

5. The DARC signal demodulation circuit assemblage of claim 1 , wherein the pilot tone regulation circuit:
is configured to:
obtain a third multiplication signal from the FM multiplex transmission signal and from the first oscillation;
obtain a fourth multiplication signal from the FM multiplex transmission signal and from the second oscillation;
obtain a fifth multiplication signal from the third and fourth multiplication signals; and
generate a control signal from the fifth multiplication signal; and

includes an oscillation generator, the oscillation generator being configured to generate the first and second oscillations, in a manner controlled by the control signal, by polynomial approximation.

6. The DARC signal demodulation circuit assemblage of claim 1 , wherein the DARC signal demodulation circuit assemblage is in an FM multiplex broadcast receiver.

7. A method for operating a Data Radio Channel (DARC) signal demodulation circuit assemblage to recover a DARC signal, containing DARC data, from a FM multiplex transmission signal, the method comprising:
obtaining a first oscillation and a second oscillation that are orthogonal to each other and are synchronous with a stereo pilot tone encompassed by the FM multiplex transmission signal;
obtaining, based on the first and second oscillations and by frequency quadruplication, a third oscillation and a fourth oscillation that are orthogonal to each other and that have quadruple the frequency of the stereo pilot tone;
obtaining a first multiplication signal from the FM multiplex transmission signal and from the third oscillation by signal multiplication;
obtaining a second multiplication signal from the FM multiplex transmission signal and from the fourth oscillation;
obtaining, by low-pass filtration, a first DARC signal component from the first multiplication signal;
obtaining a second DARC signal component from the second multiplication signal; and
obtaining the DARC signal from a frequency demodulation of the first signal component and the second DARC signal component.

8. The method of claim 7 , wherein a clock signal for obtaining the DARC data from the DARC signal is derived from the stereo pilot tone in frequency- and phase-accurate fashion with respect to the stereo pilot tone.

9. A non-transitory computer readable medium on which is stored a computer program that is executable by a processor and that, when executed, causes the processor to operate a Data Radio Channel (DARC) signal demodulation circuit assemblage to recover a DARC signal, containing DARC data, from a FM multiplex transmission signal, by performing the following:
obtaining a first oscillation and a second oscillation that are orthogonal to each other and are synchronous with a stereo pilot tone encompassed by the FM multiplex transmission signal;
obtaining, based on the first and second oscillations and by frequency quadruplication, a third oscillation and a fourth oscillation that are orthogonal to each other and have quadruple the frequency of the stereo pilot tone;
obtaining a first multiplication signal from the FM multiplex transmission signal and from the third oscillation by signal multiplication;
obtaining a second multiplication signal from the FM multiplex transmission signal and from the fourth oscillation;
obtaining, by low-pass filtration, a first DARC signal component from the first multiplication signal;
obtaining a second DARC signal component from the second multiplication signal; and
obtaining the DARC signal from a frequency demodulation of the first DARC signal component and the second DARC signal component.

10. The computer readable medium of claim 9 , wherein a clock signal for obtaining the DARC data from the DARC signal is derived from the stereo pilot tone in frequency- and phase-accurate fashion with respect to the stereo pilot tone.

11. A Data Radio Channel (DARC) signal demodulation circuit for recovering a DARC signal that includes DARC data, the circuit comprising:
a receiving interface; and
processing circuitry, wherein the processing circuitry is configured to:
receive via the receiving interface an FM multiplex transmission signal;
generate a first oscillation and a second oscillation that are orthogonal to each other and are synchronous with a stereo pilot tone encompassed by the received FM multiplex transmission signal;
generate, based on the first and second oscillations, a third oscillation and a fourth oscillation that are orthogonal to each other and have a frequency quadrupled with respect to the stereo pilot tone;
generate a first multiplication signal from the FM multiplex transmission si

Assignees

• Bosch Gmbh Robert

Inventors

• Nyenhuis Detlev

Classifications

• H04L27/2014

  in which the phase changes in a piecewise linear manner during each symbol period, e.g. minimum shift keying, fast frequency shift keying (H04L27/201 takes precedence) · CPC title

• H04L27/227 Primary

  using coherent demodulation · CPC title

• H04B1/16

  Circuits · CPC title

• H04B1/1646

  adapted for the reception of stereophonic signals · CPC title

• H04B1/30

  for homodyne or synchrodyne receivers (demodulator circuits H03D1/22) · CPC title