Method and system for smart card chip personalization

Patent metadata

Field	Value
Publication number	US-9729322-B2
Application number	US-201615093044-A
Country	US
Kind code	B2
Filing date	Apr 7, 2016
Priority date	Oct 11, 2012
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Method and system for personalizing a chip, intended to be integrated into a smart card, comprising a tester associated to an FPGA device connected to the chip, the chip being part of a wafer comprising a plurality of chips and a disposable hardware module for verifying presence of the chip on the wafer. The tester sends a first secret code to the FPGA device, which commands the chip to initiate a test mode activation. The FPGA device encrypts a second secret code by using a secret encryption algorithm parameterized with a random number received from the chip and the first secret code to obtain a first cryptogram which is sent to the chip. The chip determines a second cryptogram by carrying out a Boolean function over a result obtained by decryption of the first cryptogram using the inverse algorithm parameterized with the random number and the first secret code. The second cryptogram is compared with a result obtained by carrying out the Boolean function over the second secret code temporarily stored on the chip. The FPGA device personalizes the chip only if the second cryptogram matches the calculated result.

First claim

The invention claimed is:

1. A Field Programmable Gate Array (FPGA) device configured for personalizing at least one chip intended to be integrated into a security device, the FPGA device being connectable to a tester and to the at least one chip being part of a wafer comprising an arrangement of multiple chips, wherein the FGPA device is configured to:
receive a first secret code from the tester;
send a command to the at least one chip, the command initiating a sequence of a test mode activation;
receive a response to the command indicating presence of the at least one chip on the wafer;
receive a random number from the at least one chip;
determine a cryptogram resulting from an encryption of a second secret code by using a secret encryption algorithm parameterized with the received random number and first secret code, the second secret code being stored in a permanent memory of the FGPA device;
send the cryptogram to the at least one chip;
receive a response message from the at least one chip, the response message indicating that the test mode of the at least one chip is enabled by a successful comparison, by the at least one chip, between a decryption result of the cryptogam and a calculation result based on the second secret code temporarily stored on the at least one chip; and
perform a personalization of the at least one chip when the test mode of the at least one chip is enabled, the personalization comprising storing unique secret data on the at least one chip.

2. The FPGA device according to claim 1 , wherein the response message received from the at least one chip indicates that the test mode of the at least one chip is enabled by a successful comparison between a result obtained, by the at least one chip, by carrying out a Boolean function over the decryption result of the cryptogram obtained by using the inverse of the secret encryption algorithm parameterized with the random number and the first secret code, and the calculation result obtained by carrying out the Boolean function over the second secret code temporarily stored on the at least one chip.

3. The FPGA device according to claim 1 , further configured to access encrypted non-volatile memory of the at least one chip and to load application code into the at least one chip during the personalization.

4. The FPGA device according to claim 3 , further configured to select a predefined version of an application code stored in the encrypted non-volatile memory of the FPGA device among a plurality of versions of the application code stored in the encrypted non-volatile memory of the FPGA device.

5. The FPGA device according to claim 3 , further configured to send the application code to the at least one chip with the application code encrypted using an algorithm depending on a true random number previously produced by the at least one chip.

6. The FPGA device according to claim 1 , further provided with tamper-proof or tamper-evident modules and mechanically and electrically connected to the tester in such a way to be physically inaccessible by users of the tester during chip personalization.

7. The FPGA device according to claim 1 , further configured to transmit to the tester information comprising current state data of said FPGA device and history data of the personalized at least one chip for traceability purposes.

8. A method performed by a Field Programmable Gate Array (FPGA) device for personalizing at least one chip intended to be integrated into a security device, the FPGA device being connectable to a tester and to the at least one chip being part of a wafer comprising an arrangement of multiple chips, the method comprising:
receiving by the FPGA device a first secret code from the tester;
sending by the FPGA device a command to the at least one chip, the command initiating a sequence of a test mode activation;
receiving by the FPGA device a response to the command indicating presence of the at least one chip on the wafer;
receiving by the FPGA device a random number from the at least one chip;
determining by the FPGA device a cryptogram resulting from an encryption of a second secret code by using a secret encryption algorithm parameterized with the received random number and first secret code, the second secret code being stored in a permanent memory of the FGPA device;
sending by the FPGA device the cryptogram to the at least one chip; and
receiving by the FPGA device a response message from the at least one chip, the response message indicating that the test mode of the at least one chip is enabled by a successful comparison, by the at least one chip, between a decryption result of the cryptogam and a calculation result based on the second secret code temporarily stored on the at least one chip;
performing by the FPGA device a personalization of the at least one chip when the test mode of the at least one chip is enabled, the personalization comprising storing unique secret data on the at least one chip.

9. The method according to claim 8 , wherein the response message received from the at least one chip indicates that the test mode of the at least one chip is enabled by a successful comparison between a result obtained, by the at least one chip, by carrying out a Boolean function over the decryption result of the cryptogram obtained by using the inverse of the secret encryption algorithm parameterized with the random number and the first secret code, and the calculation result obtained by carrying out the Boolean function over the second secret code temporarily stored on the at least one chip.

10. The method according to claim 8 , further comprising accessing by the FPGA device encrypted non-volatile memory of the at least one chip and to loading application code into the at least one chip during the personalization.

11. The method according to claim 10 , further comprising selecting by the FPGA device a predefined version of an application code stored in the encrypted non-volatile memory of the FPGA device among a plurality of versions of the application code stored in the encrypted non-volatile memory of the FPGA device.

12. The method according to claim 10 , further comprising sending by the FPGA device the application code to the at least one chip with the application code encrypted using an algorithm depending on a true random number previously produced by the at least one chip.

13. The method according to claim 8 , wherein the FPGA device is further provided with tamper-proof or tamper-evident modules and mechanically and electrically connected to the tester in such a way to be physically inaccessible by users of the tester during chip personalization.

14. The method according to claim 8 , further comprising transmitting by the FPGA device to the tester information comprising current state data of said FPGA device and history data of the personalized at least one chip for traceability purposes.

Assignees

• Nagravision Sa

Inventors

• Hautier Roan
• Macchetti Marco
• Perrine Jerome

Classifications

• G06F21/31

  User authentication · CPC title

• H04L9/0869

  involving random numbers or seeds · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• H04L9/0877

  using additional device, e.g. trusted platform module [TPM], smartcard, USB or hardware security module [HSM] · CPC title

• G06F21/572 Primary

  Secure firmware programming, e.g. of basic input output system [BIOS] · CPC title