Circuit and a method for selecting a power supply

Patent metadata

Field	Value
Publication number	US-9729145-B2
Application number	US-201213494055-A
Country	US
Kind code	B2
Filing date	Jun 12, 2012
Priority date	Jun 12, 2012
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A circuit is provided, the circuit including: a first power supply terminal connected to a first p-type metal oxide semiconductor transistor; a second power supply terminal connected to a second p-type metal oxide semiconductor transistor; an output node connected between the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor; and a decision circuit connected to the first power supply terminal and the second power supply terminal, wherein the decision circuit is powered by the output node and wherein gate terminals of the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor are complementarily and actively controlled by the decision circuit.

First claim

What is claimed is:

1. A circuit, comprising:
a first power supply terminal connected to a first p-type metal oxide semiconductor transistor;
a second power supply terminal connected to a second p-type metal oxide semiconductor transistor;
an output node connected between the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor;
a decision circuit connected to the first power supply terminal and the second power supply terminal, wherein the output node powers the decision circuit and where the power to the decision circuit is substantially the same as the power from the output node, and wherein gate terminals of the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor are complementarily and actively controlled by the decision circuit; and
a biasing circuit connected to the decision circuit, wherein the biasing circuit is configured to modulate the decision speed of the decision circuit to a fast mode wherein the first power supply terminal supplies power to the circuit, and to modulate the decision speed of the decision circuit to a slow mode wherein the second power supply terminal supplies power to the circuit; and wherein the output node powers the biasing circuit.

2. The circuit according to claim 1 ,
wherein the first power supply terminal is connected to a first power supply, wherein the first power supply comprises a chip card reader device.

3. The circuit according to claim 1 ,
wherein the first power supply terminal is connected to a first power supply, wherein the first power supply comprises a chip card reader device; and
wherein the second power supply terminal is connected to a second power supply,
wherein the second power supply comprises a direct current power source.

4. The circuit according to claim 1 ,
wherein the second power supply terminal is connected to a second power supply,
wherein the second power supply comprises at least one power supply from the following group of power supplies, the group consisting of: a battery, an electrochemical cell, a fuel cell, a voltage source, a rechargeable battery.

5. The circuit according to claim 1 ,
wherein the decision circuit is configured to power supply a decision circuit output signal such that one of the first p-type metal oxide semiconductor transistor and the second p-type metal oxide semiconductor transistor is in an on-state, and the other of the first p-type metal oxide semiconductor transistor and the second p-type metal oxide semiconductor transistor is in an off-state,
wherein power is supplied to the output node by a power supply electrically connected to the p-type metal oxide semiconductor transistor in the on-state.

6. The circuit according to claim 1 ,
wherein the decision circuit is configured to compare power supplied by the first power supply terminal and power supplied by the second power supply terminal.

7. The circuit according to claim 1 ,
wherein gate terminals of the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor are complementarily and actively controlled by a decision circuit output signal,
wherein the decision circuit output signal is based on power supplied by the first power supply terminal and power supplied by the second power supply terminal.

8. The circuit according to claim 1 ,
wherein gate terminals of the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor are complementarily and actively controlled by a decision circuit output signal,
wherein the decision circuit output signal is based on a difference in power supplied by the first power supply terminal and power supplied by the second power supply terminal.

9. The circuit according to claim 1 ,
wherein the decision circuit is configured to power supply a decision circuit output signal to electrically activate one of the first p-type metal oxide semiconductor transistor and the second p-type metal oxide semiconductor transistor, and to electrically deactivate the other of the first p-type metal oxide semiconductor transistor and the second p-type metal oxide semiconductor transistor.

10. The circuit according to claim 1 , further comprising
an inverter connected between a first p-type metal oxide semiconductor transistor gate terminal and the decision circuit.

11. The circuit according to claim 10 ,
wherein the inverter is configured to invert a decision circuit output signal, such that an inverted decision circuit output signal is provided to the first p-type metal oxide semiconductor transistor gate terminal, and the decision circuit output signal is provided to the second p-type metal oxide semiconductor transistor gate terminal.

12. The circuit according to claim 1 ,
wherein one of the first power supply terminal and the second power supply terminal is configured to power an external device connected to the output node.

13. The circuit according to claim 1 ,
wherein the decision circuit comprises a comparator circuit,
wherein a first comparator circuit input terminal is connected to the first power supply terminal, and wherein a second comparator circuit input terminal is connected to the second power supply terminal.

14. The circuit according to claim 13 , further comprising
a Schmitt trigger circuit connected to the comparator circuit.

15. The circuit according to claim 14 ,
wherein a decision circuit output signal is connected to the first p-type metal oxide semiconductor transistor and the second p-type metal oxide semiconductor transistor via the Schmitt trigger circuit.

16. The circuit according to claim 1 ,
wherein the decision circuit comprises a hysteresis voltage,
wherein a decision circuit output signal is configured to electrically activate the first p-type metal oxide semiconductor transistor and not the second p-type metal oxide semiconductor transistor when power supplied by the first power supply terminal exceeds the sum of power supplied by the second power supply terminal and the hysteresis voltage.

17. The circuit according to claim 16 ,
wherein a decision circuit output signal is configured to electrically activate the second p-type metal oxide semiconductor transistor and not the first p-type metal oxide semiconductor transistor when power supplied by the second power supply terminal exceeds the sum of power supplied by the first power supply terminal and the hysteresis voltage.

18. The circuit according to claim 1 ,
wherein the biasing circuit is configured to control the decision speed of the decision circuit, depending on power supplied by the first power supply terminal and the second power supply terminal.

19. A method for selecting a power supply, the method comprising:
connecting a first power supply terminal to a first p-type metal oxide semiconductor transistor;
connecting a second power supply terminal to a second p-type metal oxide semiconductor transistor;
connecting an output node between the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor;
connecting a decision circuit to the first power supply terminal and the second power supply terminal, wherein the decision circuit is powered by the output node, and the decision circuit complementarily and actively controlling gate terminals of the first p-type metal oxide semiconductor transistor and second p-type metal oxide semiconductor transistor; and
connecting a biasing circuit t

Assignees

• Sbuell Richard
• Infineon Technologies Ag

Inventors

• Sbuell Richard

Classifications

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• G06F1/263

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• Y10T307/76

  Cross-Sectional Technologies · mapped topic