Ground fault circuit interrupter (GFCI) monitor
US-9525282-B2 · Dec 20, 2016 · US
US9728952B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9728952-B2 |
| Application number | US-201414512769-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 13, 2014 |
| Priority date | Dec 17, 2010 |
| Publication date | Aug 8, 2017 |
| Grant date | Aug 8, 2017 |
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The present invention is directed to an electrical wiring device that includes an automatic test circuit configured to commence an automatic test at a predetermined time such that a test current propagates on a test conductor. The sensor assembly provides a sensor test output responsive to the test current only if both the differential transformer and the grounded neutral transformer are operative. A fault detector circuit is configured to generate a test detection signal in response to the sensor test output only if the fault detector circuit is operable and the at least one power supply is substantially charged. A device integrity evaluation circuit includes a timer that effects a tripped state when a time measurement exceeds a threshold, the test detection signal resetting the time measurement when properly wired before the time measurement exceeds the predetermined threshold but does not reset the time measurement when miswired.
Opening claim text (preview).
What is claimed is: 1. An electrical wiring device for use in an electrical distribution system including a plurality of line conductors coupled to a source of AC power and a plurality of load conductors, comprising: a housing including a plurality of line terminals and a plurality of load terminals, the plurality of line terminals being configured to terminate the plurality of line conductors and the plurality of load terminals being configured to terminate the plurality of load conductors, the electrical wiring device being in a properly wired condition when the plurality of line conductors are terminated to the plurality of line terminals and in a miswired condition when the plurality of line conductors are terminated to the plurality of load terminals, an internal line conductor and an internal neutral conductor being disposed in the interior of the housing and coupled between the plurality of line terminals and the plurality of load terminals in a reset state and decoupled in a tripped state; a sensor assembly including a differential transformer and a grounded neutral transformer, the internal line conductor and the internal neutral conductor being routed through the differential transformer and the grounded neutral transformer; an automatic test circuit including a test conductor routed through the differential transformer and the grounded neutral transformer, the automatic test circuit being configured to commence an automatic test at a predetermined time such that a test current propagates on the test conductor, the sensor assembly providing a sensor test output responsive to the test current only if both the differential transformer and the grounded neutral transformer are operative; a protective circuit including a fault detector circuit and a power supply circuit coupled to the plurality of line terminals, the power supply circuit being charged in the reset state and charged in the tripped state and in the properly wired condition, the fault detector circuit being configured to generate a test detection signal in response to the sensor test output only if the fault detector circuit is operable and the at least one power supply is substantially charged; and a device integrity evaluation circuit coupled to the plurality of load terminals, the device integrity evaluation circuit including a timing circuit configured to provide a time measurement and a tripping stimulus to effect the tripped state when the time measurement exceeds a predetermined threshold, the test detection signal resetting the time measurement in the properly wired condition before the time measurement exceeds the predetermined threshold but does not reset the time measurement in the miswired condition. 2. The device of claim 1 , wherein the test conductor is not connected to the internal line conductor or the internal neutral conductor. 3. The device of claim 1 , further comprising a circuit interrupter assembly including a plurality of moveable contacts, the plurality of movable contacts being configured to be latched into the reset state in response to a reset stimulus and driven into the tripped state in response to the tripping stimulus. 4. The device of claim 3 , wherein the power supply circuit is coupled to the plurality of line terminals by way of a switch disposed in parallel with an impedance component, the switch being operatively coupled to a circuit interrupter assembly to open or close in response to the tripped state or the reset state. 5. The device of claim 3 , further comprising at least one circuit configured to be open circuited after AC power is initially applied to the line terminals, the at least one switch element opening and closing independently of the circuit interrupter assembly. 6. The device of claim 1 , wherein the at least one power supply is coupled to the plurality of load terminals via an isolation component. 7. The device of claim 1 , wherein the automatic test circuit is configured to process a signal derived from the source of AC power in order to establish the predetermined time. 8. The device of claim 7 , wherein the predetermined time is based on a time constant. 9. The device of claim 7 , wherein the automatic test circuit includes a resistor and a device characterized by a predetermined reactance. 10. The device of claim 1 , wherein the automatic test circuit is configured to schedule the time measurement during a predetermined portion of the AC line cycle. 11. The device of claim 1 , wherein the automatic test circuit is configured to propagate the test current on the test conductor during portions of a positive half cycle of the AC line cycle and portions of a negative half cycle of the AC line cycle. 12. The device of claim 1 , wherein the power supply circuit is coupled to an indicator circuit when the device is in the tripped state. 13. The device of claim 1 , wherein the power supply circuit is configured to substantially suppress the sensor test fault output at a predetermined time in order to prevent the test detection signal from causing a transition from the reset state to the tripped state. 14. The device of claim 1 , further comprising at least one indicator, the at least one indicator including a visual indicator configured to provide a periodic visual signal when the time measurement exceeds the predetermined threshold. 15. The device of claim 1 , wherein the power supply circuit is coupled to the plurality of line terminals by way of a switch disposed in parallel with an impedance component. 16. The device of claim 1 , further comprising a wiring state detection circuit coupled between the line terminals and configured to provide a predetermined signal if the proper wiring condition has been effected. 17. The device of claim 16 , wherein the predetermined signal includes a current flow simulating a fault condition. 18. The device of claim 1 , wherein the wiring state detection circuit assembly comprises: a first circuit coupled between the plurality of line terminals and configured to provide a predetermined response in the properly wired condition, the circuit being substantially disabled after the occurrence of the predetermined response; and a second circuit coupled between the plurality of load terminals, the second circuit being configured to provide power to the device integrity evaluation circuit from the plurality of load terminals when the device is in the miswired condition and in the tripped state. 19. The device of claim 1 , further comprising at least one circuit configured to be open circuited after AC power is initially applied to the line terminals. 20. The device of claim 19 , wherein the at least one circuit includes at least one switch element, the predetermined current flow being conducted if the at least one switch element is closed. 21. The device of claim 20 , wherein the at least one switch element includes at least one contact coupled to a printed circuit board. 22. The device of claim 1 , wherein the device integrity evaluation circuit is coupled to the plurality of load terminals by way of at least one power isolation component. 23. The device of claim 22 , wherein the at least one power isolation component includes an auxiliary switching element, the auxiliary switching element being configured to decouple the device integrity evaluation circuit from one of the plurality of line terminals when the circuit interrupter assembly is in the tripped state. 24. The device of claim 22 , wherein
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