Back-side-emitting vertical cavity surface emitting laser (VCSEL) wafer bonded to a heat-dissipation wafer, devices and methods

Patent metadata

Field	Value
Publication number	US-9728934-B2
Application number	US-201514841569-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A wafer-to-wafer bonded arrangement is provided comprising a VCSEL wafer and a highly thermally-conductive (HTC) wafer that are bonded together with the front side of the VCSEL wafer bonded to the HTC wafer. The VCSEL wafer is fabricated to include, at least initially, a native substrate. The HTC wafer includes a thermally-conductive, non-native substrate. All or a portion of the native substrate may be removed after performing wafer-to-wafer bonding. In effect, the HTC wafer becomes the substrate of the bonded pair. During operation of VCSEL dies diced from the bonded wafer, heat generated by the dies flows into the non-native substrate where the heat spreads out and is dissipated. Laser light generated by the VCSEL die is emitted through the back side of the VCSEL die.

First claim

What is claimed is:

1. A wafer-to-wafer bonded arrangement comprising:
a highly thermally-conductive (HTC) wafer, the HTC wafer comprising a non-native substrate; and
a vertical cavity surface emitting laser (VCSEL) wafer having a front side and a back side, the VCSEL wafer comprising:
an epitaxial (epi) structure having a first side and a second side, the epi structure comprising a first distributed Bragg reflector (DBR) adjacent the first side of the epi structure, a second DBR adjacent the second side of the epi structure, and one or more layers comprising a quantum well (QW) region disposed in between the first DBR and the second DBR, the first DBR having a first electrical conductivity type and the second DBR having a second electrical conductivity type that is different from the first electrical conductivity type; and
a first contact metal layer disposed on the front side of the VCSEL wafer and in contact with the first DBR, the first contact metal layer being bonded to a top surface of the HTC wafer, wherein the VCSEL wafer has a plurality of first trenches formed therein that pass through the first contact metal layer, through the first side of the epi structure and extend a distance into the epi structure without passing through the epi structure to the second side of the epi structure.

2. The wafer-to-wafer bonded arrangement of claim 1 , wherein the VCSEL wafer further comprises:
a native substrate having a top surface and a bottom surface, the bottom surface of the native substrate being adjacent the second side of the epi structure, the non-native substrate being made of a material that has a higher thermal conductivity than a thermal conductivity of a material of which the native substrate is made.

3. The wafer-to-wafer bonded arrangement of claim 2 , wherein the materials of which the native and non-native substrates are made have coefficients of thermal expansion (CTEs) that are closely matched.

4. The wafer-to-wafer bonded arrangement of claim 2 , wherein the materials of which the native and non-native substrates are made have coefficients of thermal expansion (CTEs) that differ by less than 3 parts per million per degree Celsius.

5. The wafer-to-wafer bonded arrangement of claim 2 , wherein the material of which the non-native substrate is made is Molybdenum.

6. The wafer-to-wafer bonded arrangement of claim 2 , wherein the material of which the non-native substrate is made comprises multiple layers of different materials.

7. The wafer-to-wafer bonded arrangement of claim 2 , wherein the material of which the native substrate is made is Gallium Arsenide (GaAs).

8. The wafer-to-wafer bonded arrangement of claim 1 , wherein the VCSEL wafer comprises a plurality of VCSEL dies, and wherein each VCSEL die has one of the first trenches formed therein about a periphery of the respective VCSEL die.

9. The wafer-to-wafer bonded arrangement of claim 1 , wherein the VCSEL wafer was fabricated to include a native substrate that was subsequently removed after the bonding of the first contact metal layer to the top surface of the HTC wafer, the non-native substrate being made of a material that has a higher thermal conductivity than a thermal conductivity of a material of which the native substrate is made.

10. The wafer-to-wafer bonded arrangement of claim 9 , wherein the material of which the non-native substrate is made is Molybdenum.

11. The wafer-to-wafer bonded arrangement of claim 9 , wherein the material of which the non-native substrate is made comprises multiple layers of different materials.

12. The wafer-to-wafer bonded arrangement of claim 9 , wherein the material of which the native substrate is made is Gallium Arsenide (GaAs).

13. The wafer-to-wafer bonded arrangement of claim 9 , wherein the materials of which the native and non-native substrates are made have coefficients of thermal expansion (CTEs) that are closely matched.

14. The wafer-to-wafer bonded arrangement of claim 9 , wherein the materials of which the native and non-native substrates are made have coefficients of thermal expansion (CTEs) that differ by less than 3 parts per million per degree Celsius.

15. The wafer-to-wafer bonded arrangement of claim 9 , wherein the VCSEL wafer comprises a plurality of VCSEL dies, and wherein each of the first trenches is formed about a periphery of a respective VCSEL die.

16. The wafer-to-wafer bonded arrangement of claim 15 , wherein the VCSEL wafer has at least one second trench formed therein, each second trench passing through the first contact metal layer and through the epi structure such that the second trench is viewable by an imaging device from the back side of the VCSEL wafer.

17. The wafer-to-wafer bonded arrangement of claim 16 , wherein the VCSEL wafer has a plurality of the second trenches formed therein.

18. The wafer-to-wafer bonded arrangement of claim 1 , wherein the VCSEL wafer comprises a plurality of VCSEL dies, wherein the epi structure and the first contact metal layer extend through all of the VCSEL dies, and wherein the first DBR of each VCSEL has a non-planar mesa structure formed therein, each mesa structure including sloped side walls and a generally flat top, the flat top of each mesa structure being in contact with the first contact metal layer.

19. The wafer-to-wafer bonded arrangement of claim 18 , wherein each VCSEL die comprises at least one VCSEL.

20. The wafer-to-wafer bonded arrangement of claim 19 , wherein each VCSEL die comprises an array of VCSELs.

21. The wafer-to-wafer bonded arrangement of claim 1 , wherein the bond is a thermal compression bond.

22. The wafer-to-wafer bonded arrangement of claim 1 , wherein the non-native substrate is made of a material that is electrically conductive.

23. A back-side-emitting vertical cavity surface emitting laser (VCSEL) chip comprising:
a highly thermally-conductive (HTC) substrate; and
a vertical cavity surface emitting laser (VCSEL) die having a front side and a back side, the VCSEL die comprising:
an epitaxial (epi) structure having a first side and a second side, the epi structure comprising a first distributed Bragg reflector (DBR) adjacent the first side of the epi structure, a second DBR adjacent the second side of the epi structure, and one or more layers comprising a quantum well (QW) region disposed in between the first DBR and the second DBR, the first DBR having a first electrical conductivity type and the second DBR having a second electrical conductivity type that is different from the first electrical conductivity type; and
a first contact metal layer disposed on the front side of the VCSEL die and in contact with the first DBR, the first contact metal layer being bonded to a top surface of the HTC substrate or to a metal layer disposed on the top surface of the HTC substrate, wherein laser light produced by the VCSEL die is emitted from the VCSEL chip through the back side of the VCSEL die, wherein the VCSEL die has a first trench formed about a periphery thereof, the first trench passing through the first contact metal layer, through the first side of the epi structure and extending a distance into the epi structure without passing through the epi structure to the second side of the epi structure.

24. The back-side-emitting VCSEL chip of claim 23 , wherein the VCSEL chip further comprises:
a native substrate having a top surface and a bottom surface, the bottom surface of the native substrate being adjacent the first side

Assignees

• Avago Technologies General Ip

Inventors

• Wang Tak Kui
• Su Chung-Yi

Classifications

• H01S5/0201

  Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth · CPC title

• H01S5/0203

  Etching · CPC title

• H01S5/18377

  comprising layers of different kind of materials, e.g. combinations of semiconducting with dielectric or metallic layers · CPC title

• H01S5/0217

  Removal of the substrate · CPC title

• H01S5/0216

  using an intermediate compound, e.g. a glue or solder · CPC title