Aligned carbon nanotubes for use in high performance field effect transistors

Patent metadata

Field	Value
Publication number	US-9728734-B2
Application number	US-201615154170-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	Feb 11, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

High density films of semiconducting single-walled carbon nanotubes having a high degree of nanotube alignment are provided. Also provided are methods of making the films and field effect transistors (FETs) that incorporate the films as conducting channel materials. The single-walled carbon nanotubes are deposited from a thin layer of organic solvent containing solubilized single-walled carbon nanotubes that is spread over the surface of an aqueous medium, inducing evaporative self-assembly upon contacting a solid substrate.

First claim

What is claimed is:

1. A field effect transistor comprising:
a source electrode;
a drain electrode;
a gate electrode;
a conducting channel in electrical contact with the source electrode and the drain electrode, the conducting channel comprising a film comprising aligned s-SWCNTs; and
a gate dielectric disposed between the gate electrode and the conducting channel,
wherein the field effect transistor has a channel length of up to about 9 μm and an on-conductance per width of at least 5 μS μm −1 and an on/off ratio per width of at least 1×10 5 .

2. The transistor of claim 1 having an on-conductance per width of at least 7 μS μm −1 and an on/off ratio per width of at least 1.5×10 5 .

3. The transistor of claim 1 having an on-conductance per width of at least 10 μS μm −1 and an on/off ratio per width of at least 2×10 5 .

4. The transistor of claim 1 , wherein the single-walled carbon nanotube linear packing density in the film is at least 40 single-walled carbon nanotubes/μm.

5. The transistor of claim 1 , wherein the single-walled carbon nanotube linear packing density in the film is at least 50 single-walled carbon nanotubes/μm.

6. The transistor of claim 1 , wherein the film has a semiconducting single-walled carbon nanotube purity level of at least 99.9%.

7. The transistor of claim 1 , wherein the s-SWCNTs are wrapped in a semiconductor-selective polymer.

8. The transistor of claim 1 , wherein the single-walled carbon nanotube linear packing density in the film is at least 50 single-walled carbon nanotubes/μm, the film has a semiconducting single-walled carbon nanotube purity level of at least 99%, the transistor has a channel length in the range from 400 nm to 4 μm, and the transistor has an on-conductance per width of at least 10 μS μm −1 and an on/off ratio per width of at least 1×10 5 .

9. The transistor of claim 1 , wherein the single-walled carbon nanotube linear packing density in the film is at least 50 single-walled carbon nanotubes/μm, the film has a semiconducting single-walled carbon nanotube purity level of at least 99%, the transistor has a channel length of no greater than 400 nm, and the transistor has an on-conductance per width of at least 20 μS μm −1 and an on/off ratio per width of at least 1×10 5 .

10. The transistor of claim 1 , wherein the thickness of the film corresponds to no more than a bilayer of the s-SWCNTs.

11. A field effect transistor comprising:
a source electrode;
a drain electrode;
a gate electrode;
a conducting channel in electrical contact with the source electrode and the drain electrode, the conducting channel comprising a film comprising aligned s-SWCNTs; and
a gate dielectric disposed between the gate electrode and the conducting channel,
wherein the field effect transistor has a channel length of at least 9 μm and an on-conductance per width of at least 5 μS μm −1 and an on/off ratio per width of at least 1×10 6 .

12. The transistor of claim 11 , wherein the single-walled carbon nanotube linear packing density in the film is at least 40 single-walled carbon nanotubes/μm.

13. The transistor of claim 11 , wherein the single-walled carbon nanotube linear packing density in the film is at least 50 single-walled carbon nanotubes/μm.

14. The transistor of claim 13 , wherein the film has a semiconducting single-walled carbon nanotube purity level of at least 99.9%.

15. The transistor of claim 11 , wherein the film has a semiconducting single-walled carbon nanotube purity level of at least 99.9%.

16. The transistor of claim 1 , wherein the s-SWCNTs are wrapped in a semiconductor-selective polymer.

17. The transistor of claim 1 , wherein the source electrode and the drain electrode are metal electrodes.

18. The transistor of claim 11 , wherein the source electrode and the drain electrode are metal electrodes.

19. The transistor of claim 9 , wherein the transistor has an on-conductance per width of at least 60 μS μm −1 and an on/off ratio per width of at least 2×10 5 .

20. The transistor of claim 11 , wherein the transistor has an on-conductance per width of at least 7 μS μm −1 and an on/off ratio per width of at least 2×10 6 .

Assignees

• Wisconsin Alumni Res Found

Inventors

• Arnold Michael Scott
• Gopalan Padma
• Brady Gerald Joseph
• Joo Yongho

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• C01B2202/02

  Single-walled nanotubes · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• C01B2202/08

  Aligned nanotubes · CPC title

• C01B32/168

  After-treatment · CPC title