Semiconductor devices having a spacer on an isolation region

Patent metadata

Field	Value
Publication number	US-9728643-B2
Application number	US-201514974018-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Apr 1, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A semiconductor device including a fin active region protruding from a substrate and an isolation region defining the fin active region, a gate pattern intersecting the fin active region and the isolation region, and gate spacer formed on a side surface of the gate pattern and extending onto a surface of the isolation region is provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin active region protruding from a substrate and an isolation region defining the fin active region;
a gate pattern intersecting the fin active region and the isolation region;
a gate spacer formed on a side surface of the gate pattern and configured to extend onto a surface of the isolation region; and
a source/drain region including a portion protruding, from the fin active region adjacent to the gate pattern, the portion of the source/drain region extending in a horizontal direction,
wherein the gate spacer on the isolation region and the portion of the source/drain region define an air space therebetween.

2. The semiconductor device of claim 1 , wherein
the gate spacer comprises an inner spacer having an etch selectivity with respect to the isolation region and an outer spacer having an etch selectivity with respect to the isolation region and the inner spacer, and
a portion of the outer spacer on the isolation region is between the air space and the inner spacer.

3. The semiconductor device of claim 1 , wherein the air space is spaced apart from the isolation region.

4. The semiconductor device of claim 1 , wherein the gate spacer on the isolation region has a U-shaped sectional view.

5. The semiconductor device of claim 1 , further comprising:
a capping spacer formed on the gate spacer on the isolation region,
wherein the capping spacer is not formed on a top surface of the source/drain region.

6. The semiconductor device of claim 1 , wherein the gate pattern on the fin active region comprises:
an interface insulating layer formed directly on the fin active region;
a gate insulating layer formed on the interface insulating layer;
a gate barrier layer formed on the gate insulating layer; and
a gate electrode formed on the gate barrier layer.

7. The semiconductor device of claim 1 , wherein the gate pattern on the isolation region comprises:
a gate insulating layer formed directly on the isolation region;
a gate barrier layer formed on the gate insulating layer; and
a gate electrode formed on the gate barrier layer.

8. A semiconductor device comprising:
isolation regions defining fin active regions;
gate patterns formed on the fin active regions and the isolation regions; and
gate spacers formed on side walls of the gate patterns,
wherein the gate spacers extend onto the isolation regions between the fin active regions and each of the gate spacers has U-shaped sectional views.

9. The semiconductor device of claim 8 , wherein the gate spacers comprise:
inner spacers contacting the gate patterns and the isolation regions and including silicon nitride; and
outer spacers including carbon to have an etch selectivity with respect to the inner spacers.

10. The semiconductor device of claim 8 , wherein each of the gate patterns comprises:
a gate insulating layer formed directly on the isolation region;
a gate barrier layer formed on the gate insulating layer; and
a gate electrode formed on the gate barrier layer.

11. The semiconductor device of claim 10 , wherein each of the gate patterns further comprises an interface insulating layer between the fin active region and the gate insulating layer.

12. The semiconductor device of claim 8 , further comprising:
source/drain regions protruding from insides of the fin active regions between the gate patterns; and
contact patterns formed on the source/drain regions,
wherein the source/drain regions are connected with each other in a bridge shape,
wherein each of the contact patterns comprises a silicide layer formed on the source/drain region, a contact barrier layer formed on the silicide layer, and a contact plug formed on the contact barrier layer.

13. The semiconductor device of claim 8 , wherein the gate spacers on the isolation regions between the fin active regions completely cover the isolation regions between the fin active regions.

14. A semiconductor device comprising:
fin active regions extending in a first direction and isolation regions formed between the fin active regions;
gate patterns extending in a second direction perpendicular to the first direction to intersect the fin active regions and the isolation regions;
capping spacers on the isolation regions between the gate patterns;
gale spacers on sidewalls of the gate patterns; and
source/drain regions formed in the fin active regions between the gate patterns,
wherein the gate spacers cover the isolation regions between the gate patterns.

15. The semiconductor device of claim 14 , wherein the gate spacers formed on facing sidewalls of adjacent gate patterns are integrated to be materially contiguous.

16. The semiconductor device of claim 15 , wherein the gate spacers comprises:
inner spacers directly formed on the sidewalls of the gate patterns; and
outer spacers formed on outer sidewalls of the inner spacers,
wherein the inner spacers contacting the isolation regions and the source/drain regions.

17. The semiconductor device of claim 14 , wherein the capping spacers have concave bowl shapes and are not formed on the sidewalls of the gate patterns.

18. The semiconductor device of claim 14 , wherein the gate spacers completely cover the isolation regions between the fin active regions.

19. The semiconductor device of claim 14 , wherein the gate spacers on the isolation regions and the source/drain regions define air spaces therebetween, the air spaces being spaced apart from the isolation regions.

Assignees

• Park Byungjae
• Shin Heonjong
• Cho Hagju
• Yeo Kyounghwan
• Samsung Electronics Co Ltd

Inventors

• Park Byungjae
• Shin Heonjong
• Cho Hagju
• Yeo Kyounghwan

Classifications

• H01L29/66545

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/41791

  Electricity · mapped topic

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title