Semiconductor device with one-side-contact and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9728638-B2
Application number	US-201514981306-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Sep 30, 2009
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of active regions, each configured to have a doped conductive layer pattern doped with an impurity for forming a cell junction, the plurality of the active regions being separated from one another by trenches;
a side contact configured to be connected to a sidewall of the doped conductive layer pattern of the active region; and
metal bit lines, each configured to be connected to the side contact and fill a portion of each trench,
wherein only the doped conductive layer pattern is formed between the metal bit lines.

2. The semiconductor device of claim 1 , wherein the active regions further comprise an undoped conductive layer pattern formed over the doped conductive layer pattern.

3. The semiconductor device of claim 1 , wherein the doped conductive layer pattern comprises a silicon epitaxial layer.

4. The semiconductor device of claim 1 , wherein the impurity is an N-type impurity.

5. The semiconductor device of claim 1 , wherein the impurity is doped in a doping concentration ranging from approximately 1E19 atoms/cm 3 to approximately 1E22 atoms/cm 3 .

6. The semiconductor device of claim 1 , wherein the active regions form line-shaped pillars, and the side contact is formed in a line shape on a sidewall of the doped conductive layer pattern.

7. The semiconductor device of claim 1 , wherein the side contact comprises a metal silicide.

8. The semiconductor device of claim 1 , wherein upper surfaces of the doped conductive layer pattern and the metal bit lines are formed to have the same level.

Assignees

• Sk Hynix Inc

Inventors

• Lee Jin-Ku
• Lee Young-Ho
• Lee Mi-Ri

Classifications

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H01L27/10885

  Electricity · mapped topic

• H01L27/10888

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic