Generation of multiple diameter nanowire field effect transistors

Patent metadata

Field	Value
Publication number	US-9728619-B2
Application number	US-201213610266-A
Country	US
Kind code	B2
Filing date	Sep 11, 2012
Priority date	May 12, 2010
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

First claim

What is claimed is:

1. A system, comprising:
a wafer, including a silicon-on-insulator (SOI) structure disposed on a buried oxide (BOX) layer, the wafer having a first region and a second region,
the first region having a pair of first SOI pads connected via a first plurality of first nanowire channels formed therein in a first parallel, ladder-like formation, one of the first SOI pads comprising a first exterior face, and
the second region having a pair of second SOI pads connected via a second plurality of second nanowire channels formed therein in a second parallel, ladder-like formation, which is oriented in parallel and in phase with the first parallel, ladder-like formation such that corresponding ones of the first and second nanowire channels respectively extend longitudinally along a same linear path, one of the second SOI pads comprising a second exterior face; and
an entirely removable silicon nitride mask directly covering respective entireties of top surfaces and side surfaces of the first SOI pads and the first nanowire channels in only the first region and preventing a thinning of the second SOI pads and the second nanowire channels in the second region due to oxidation from having effect at the top and side surfaces of the first SOI pads and the first nanowire channels in the first region, wherein:
none of the SOI pads or nanowire channels of the first or the second region directly contact any of the SOI pads or nanowire channels of the second or the first region, respectively, such that the first and second exterior faces are disposed in parallel to oppositely face one another at a distance.

2. A system, comprising:
a silicon-on-insulator (SOI) wafer having a first region with a first SOI pad pair connected via first nanowire channels formed therein in a first parallel, ladder-like arrangement and a second region with a second SOI pad pair connected via second nanowire channels formed therein in a second parallel, ladder-like arrangement oriented in parallel and in phase with the first parallel, ladder-like formation such that corresponding ones of the first and second nanowire channels respectively extend longitudinally along a same linear path; and
an entirely removable silicon nitride mask directly covering respective entireties of top surfaces and side surfaces of the SOI pads and nanowire channels in only the first region and preventing a thinning of the SOI pads and nanowire channels in the second region due to oxidation from having a same effect in the first region, wherein:
none of the SOI pads or nanowire channels of the first or the second region directly contact any of the SOI pads or nanowire channels of the second or the first region, respectively.

3. A system, comprising:
a silicon-on-insulator (SOI) wafer having a first region and a second region;
a first SOI pad pair connected via first nanowire channels formed in the first region in a first parallel, ladder-like arrangement;
a second SOI pad pair connected via second nanowire channels formed in the second region in a second parallel, ladder-like arrangement,
the first and second parallel, ladder-like arrangements being oriented in parallel and in phase with each other such that corresponding ones of the first and second nanowire channels respectively extend longitudinally along a same linear path,
wherein none of the SOI pads or nanowire channels of the first region directly contact any of the SOI pads or nanowire channels of the second region; and
a mask directly covering respective entireties of top surfaces and side surfaces of the first SOI pad pair and the first nanowire channels in only the first region.

Assignees

• Bangsaruntip Sarunya
• Cohen Guy M
• Sleight Jeffrey W
• IBM

Inventors

• Bangsaruntip Sarunya
• Cohen Guy M
• Sleight Jeffrey W

Classifications

• H01L29/0665

  Electricity · mapped topic

• H01L29/66439

  Electricity · mapped topic

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L29/42392 Primary

  Electricity · mapped topic