Interconnect etch with polymer layer edge protection

Patent metadata

Field	Value
Publication number	US-9728518-B2
Application number	US-201414231997-A
Country	US
Kind code	B2
Filing date	Apr 1, 2014
Priority date	Apr 1, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.

First claim

What is claimed is:

1. A method of manufacturing, comprising:
applying a polymer layer to a passivation structure of a semiconductor workpiece, the semiconductor workpiece having first and second semiconductor chips separated by a dicing street;
patterning a first opening in the polymer layer with opposing edges pulled back from the dicing street;
applying a mask over the first opening; and
etching a first portion of the passivation structure while using the polymer layer as an etch mask.

2. The method of claim 1 , comprising laser cutting a trench in the semiconductor workpiece at the dicing street.

3. The method of claim 2 , comprising mechanically dicing the first and second chips from the semiconductor workpiece.

4. The method of claim 1 , wherein the polymer layer comprises polyimide or benzocyclobutene.

5. The method of claim 1 , comprising forming an underbump metallization structure in a second opening in the polymer layer and a solder interconnect structure on the underbump metallization structure.

6. The method of claim 1 , wherein the mask comprises a third opening within the first opening, the third opening exposing a second portion of the passivation structure.

7. The method of claim 6 , comprising etching the second portion of the passivation structure.

8. A method of manufacturing, comprising:
applying a polyimide layer to a passivation structure of a silicon wafer, the silicon wafer having first and second semiconductor chips separated by a dicing street;
patterning a first opening in the polyimide layer with opposing edges pulled back from the dicing street and second opening exposing a first portion of the passivation structure;
applying a mask over the first opening; and
etching the first portion of the passivation structure to expose an underlying portion of the silicon wafer while using the polyimide layer as an etch mask.

9. The method of claim 8 , comprising laser cutting a trench in the silicon wafer at the dicing street, the trench tracking the layout of the dicing street.

10. The method of claim 9 , comprising mechanically dicing the first and second chips from the silicon wafer.

11. The method of claim 8 , comprising forming an underbump metallization structure in the second opening in the polymer layer and a solder interconnect structure on the underbump metallization structure.

12. The method of claim 8 , wherein the mask comprises a third opening within the first opening, the third opening exposing a second portion of the passivation structure.

13. The method of claim 12 , comprising etching the second portion of the passivation structure.

14. The method of claim 5 , wherein the solder interconnect structure comprises a solder bump or conductive pillar.

15. The method of claim 1 , wherein the polymer layer contains a photoactive compound, the patterning of the first opening comprising exposing and developing the polymer layer.

16. The method of claim 1 , wherein the first opening in the polymer layer is patterned by etching.

17. The method of claim 8 , wherein the polyimide layer contains a photoactive compound, the patterning of the first opening comprising exposing and developing the polyimide layer.

18. The method of claim 8 , wherein the first opening in the polyimide layer is patterned by etching.

19. The method of claim 11 , wherein the solder interconnect structure comprises a solder bump or conductive pillar.

Assignees

• Topacio Roden R
• Ati Technologies Ulc

Inventors

• Topacio Roden R

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title