Method for producing a capacitor

Patent metadata

Field	Value
Publication number	US-9728337-B2
Application number	US-201314416978-A
Country	US
Kind code	B2
Filing date	Jul 12, 2013
Priority date	Jul 25, 2012
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.

First claim

The invention claimed is:

1. A method for producing a capacitor stack in a portion of a substrate, the method comprising:
forming a cavity along a thickness of the portion of the substrate from an upper surface of the substrate;
depositing a plurality of layers for the capacitor stack onto a wall of the cavity and onto the upper surface of the substrate, the deposited plurality of layers covering the upper surface and including a first layer of conductive material configured to form at least part of an upper electrode of the capacitor stack;
forming at least one additional capacitor stack by successive depositions, above the first layer of conductive material, of a first layer of insulating material and a second layer of conductive material; and
removing material from the deposited plurality of layers covering said upper surface, and from the successive depositions, until the upper surface of the substrate is reached,
wherein the forming of the cavity comprises forming at least one trench and, associated with the at least one trench, at least one box, the at least one trench comprising a trench outlet that opens into the at least one box, the at least one box comprising a box outlet that opens at the surface of the upper surface, and the box outlet being shaped so as to be larger than the trench outlet.

2. The method according to claim 1 , wherein the forming the at least one box comprises forming a bottom wall of the at least one box located in a same plane as the trench outlet and having a larger section than that of the trench outlet.

3. The method according to claim 2 , wherein the at least one box is formed as a rectangular parallelepiped or is cylindrical.

4. The method according to claim 1 , wherein the at least one trench is formed with a circular cross-section transverse to a thickness direction of the substrate.

5. The method according to claim 1 , wherein the at least one trench is formed with a rectangular or square cross-section transverse to a thickness of the substrate.

6. The method according to claim 1 ,
wherein the at least one box is formed with an aspect ratio smaller than 1 between a dimension of the at least one box along the thickness of the portion of the substrate and a dimension transverse to a direction of the thickness, and
wherein the at least one trench is formed with an aspect ratio greater than 1 between the dimension along the thickness of the portion of the substrate and the dimension transverse to the direction of the thickness.

7. The method according to claim 1 , wherein the deposited plurality of layers for the capacitor stack comprises, successively above the wall of the cavity, a third layer of conductive material configured to form at least a part of a bottom electrode of the capacitor stack; a second layer of insulating material; and the first layer of conductive material configured to form the at least part of the upper electrode of the capacitor stack.

8. The method according to claim 7 , further comprising etching partially the first layer of conductive material and the third layer of conductive material so that the first and the third layers of conductive material stop at a lower level than that of the second layer of insulating material along a thickness direction of the substrate.

9. The method according to claim 7 , wherein the deposited plurality of layers further comprises a third layer of insulating material located above the wall of the cavity and under the third layer of conductive material.

10. The method according to claim 1 ,
wherein a lower electrode of the capacitor stack is at least partly formed from the portion of the substrate, and
wherein the deposited plurality of layers comprises, successively above the wall of the cavity, a second layer of insulating material and the first layer of conductive material configured to form the at least part of the upper electrode of the capacitor stack.

11. The method according to claim 10 , further comprising etching partially the first layer of conductive material so that the first layer of conductive material stops at a lower level than that of the second layer of insulating material along a thickness direction of the substrate.

12. The method according to claim 1 , wherein the forming the at least one box comprises forming a flared box side wall flaring towards the box outlet.

13. The method according to claim 12 , wherein the forming a flared box side wall comprises forming, on the flared box side wall, at least one landing at an intermediate level between the trench outlet and the box outlet along the thickness of the portion of the substrate, with the at least one landing configured to define two box stages.

14. The method according to claim 13 , wherein the successive depositions to form the at least one additional capacitor stack are configured to preserve a residual space defined by the additional capacitor stack.

15. The method according to claim 14 , wherein as many box stages as capacitor stacks are formed.

16. The method according to claim 15 ,
wherein the at least one additional capacitor stack is formed above the first layer of conductive material to form at least in part the upper electrode of the capacitor stack,
wherein a depth of a stage located directly under the box outlet along the thickness of the portion of the substrate is:
greater than a sum of a thickness of the lower electrode of the capacitor stack and of the second layer of insulating material, and
less than or equal to a thickness of the capacitor stack; and

wherein a depth of another stage located directly under the stage located directly below the box outlet along the thickness of the portion of the substrate is:
greater than a sum of thicknesses of the upper electrode of the capacitor stack and of the first layer of insulating material of the at least one additional capacitor stack, and
less than or equal to a sum of thicknesses of the at least one additional capacitor stack and of the upper electrode of the capacitor stack.

17. The method according to claim 16 , further comprising forming at least one second additional capacitor stack over the at least one additional capacitor stack,
wherein, for each second additional capacitor stack of the at least one second additional capacitor stack, an additional stage is formed at a greater depth level relative than that of an upper stage corresponding to a previous additional capacitor stack, with a depth of the additional stage being:
greater than a sum of thicknesses of an additional layer of conductive material of the previous additional capacitor stack and of an additional layer of insulating material of the at least one second additional capacitor stack, and
less than or equal to a sum of thicknesses of said at least one second additional capacitor stack and of an additional layer of conductive material of the previous additional capacitor stack.

18. The method according to claim 1 , wherein the third layer of conductive material and the second layer of conductive material of the at least one additional capacitor stack are electrically connected to form a lower electrode.

19. The method according to claim 1 , wherein the substrate and the second layer of conductive material of at the least one additional capacitor stack are electrically connected to form a lower electrode.

20. The method according to claim 1 , wherein the deposited plurality of layers comprises a non-conforming deposition of at least one layer.

21. The method according to claim 20 ,

Assignees

• Commissariat Energie Atomique
• St Microelectronics Sa

Inventors

• Lamy Yann
• Guiller Olivier
• Joblot Sylvain

Classifications

• H01G4/38

  Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

• H01G4/33 Primary

  Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H01G4/306 Primary

  made by thin film techniques · CPC title

• H01L28/91

  Electricity · mapped topic