Method for manufacturing a ceramic laminated body

US9728333B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9728333-B2
Application numberUS-201514614476-A
CountryUS
Kind codeB2
Filing dateFeb 5, 2015
Priority dateAug 7, 2012
Publication dateAug 8, 2017
Grant dateAug 8, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A laminated ceramic capacitor that includes a ceramic laminated body having a stacked plurality of ceramic dielectric layers and a plurality of internal electrodes opposed to each other with the ceramic dielectric layers interposed therebetween, and external electrodes on the outer surface of the ceramic laminated body and electrically connected to the internal electrodes. The internal electrodes contain Ni and Sn, a proportion of the Sn/(Ni+Sn) ratio is 0.001 or more in molar ratio is 75% or more in a region of the internal electrode at a depth of 20 nm from a surface opposed to the ceramic dielectric layer, and the proportion of the Sn/(Ni+Sn) ratio is 0.001 or more in molar ratio is less than 40% in a central region in a thickness direction of the internal electrode.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for manufacturing a ceramic laminated body, the method comprising: providing a plurality of unfired ceramic dielectric layers containing a ceramic material powder; providing a plurality of unfired internal electrode patters, the plurality of unfired internal electrode patters being in the form of a conductive paste containing a Sn constituent blended common material, the Sn constituent blended common material containing a Sn constituent blended with a ceramic material which has a same composition as that of the ceramic material powder of the unfired ceramic dielectric layers; alternately stacking the plurality of unfired ceramic dielectric layers and the plurality of unfired internal electrode patterns so as to form an unfired ceramic laminated body; and firing the unfired ceramic laminated body at 1200° C. for 20 minutes after increasing the temperature at a rate of temperature increase of 20° C./min in a reducing atmosphere of H 2 —N 2 —H 2 O gas with an oxygen partial pressure of 10 −10 to 10 −12 MPa to obtain a fired ceramic laminated body having a plurality of alternately stacked fired ceramic dielectric layers and internal electrodes, wherein the internal electrodes contain Ni and Sn, 75% or more of a first region extending to a depth of 20 nm from a surface of an internal electrode opposed to a fired ceramic dielectric layer of the plurality of alternately stacked fired ceramic dielectric layers and internal electrodes has a first molar ratio of Sn to a total amount of Sn and Ni of 0.001 or more, and 40% or less of a second region extending from the depth of 20 nm or more from the surface of the internal electrode in a thickness direction of the internal electrode has a second molar ratio of Sn to the total amount of Sn and Ni of 0.001 or more. 2. The method for manufacturing the ceramic laminated body according to claim 1 , further comprising forming an external electrode on the outer surface of the ceramic laminated body and electrically connected to the internal electrodes.

Assignees

Inventors

Classifications

  • Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

  • Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00 · CPC title

  • Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • Form of non-self-supporting electrodes · CPC title

  • Fried electrodes · CPC title

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Frequently asked questions

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What does patent US9728333B2 cover?
A laminated ceramic capacitor that includes a ceramic laminated body having a stacked plurality of ceramic dielectric layers and a plurality of internal electrodes opposed to each other with the ceramic dielectric layers interposed therebetween, and external electrodes on the outer surface of the ceramic laminated body and electrically connected to the internal electrodes. The internal electrod…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H01G4/008. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 08 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).