Spin transfer torque memory (STTM) device with half-metal and method to write and read the device

Patent metadata

Field	Value
Publication number	US-9728238-B2
Application number	US-201113996500-A
Country	US
Kind code	B2
Filing date	Dec 19, 2011
Priority date	Dec 19, 2011
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Spin transfer torque memory (STTM) devices with half-metals and methods to write and read the devices are described. For example, a magnetic tunneling junction includes a free magnetic layer, a fixed magnetic layer, and a dielectric layer disposed between the free magnetic layer and the fixed magnetic layer. One or both of the free magnetic layer and the fixed magnetic layer includes a half-metal material at an interface with the dielectric layer.

First claim

What is claimed is:

1. A magnetic tunneling junction, comprising:
a free magnetic layer;
a fixed magnetic layer; and
a dielectric layer disposed between the free magnetic layer and the fixed magnetic layer, wherein one or both of the free magnetic layer and the fixed magnetic layer comprises a half-metal material at an interface with the dielectric layer, and wherein the half-metal material consists of Fe 3 Si.

2. The magnetic tunneling junction of claim 1 , wherein only the fixed magnetic layer comprises a half-metal material at the interface with the dielectric layer.

3. The magnetic tunneling junction of claim 2 , wherein the fixed magnetic layer further comprises a ferroelectric material adjacent the half-metal material, distal from the interface of the fixed magnetic layer with the dielectric layer.

4. The magnetic tunneling junction of claim 2 , wherein the free magnetic layer comprises a ferroelectric material.

5. The magnetic tunneling junction of claim 4 , wherein the free magnetic layer further comprises a half-metal material adjacent the ferroelectric material, distal from the interface of the free magnetic layer with the dielectric layer.

6. The magnetic tunneling junction of claim 1 , wherein the half-metal material is a ferromagnetic metal alloy based on a Heusler phase.

7. The magnetic tunneling junction of claim 1 , further comprising an anti-ferromagnetic layer adjacent the fixed magnetic layer, distal from the interface of the fixed magnetic layer with the dielectric layer.

8. A non-volatile memory device, comprising:
a first electrode;
a fixed magnetic layer disposed above the first electrode;
a free magnetic layer disposed above the fixed magnetic layer;
a second electrode disposed above the free magnetic layer;
a dielectric layer disposed between the free magnetic layer and the fixed magnetic layer, wherein one or both of the free magnetic layer and the fixed magnetic layer comprises a half-metal material at an interface with the dielectric layer, and wherein the half-metal material is Fe 3 Si; and
a transistor electrically connected to the first or the second electrode, a source line, and a word line.

9. The non-volatile memory device of claim 8 , wherein the transistor is electrically connected to the first electrode, the source line, and the word line.

10. The non-volatile memory device of claim 8 , wherein the transistor is electrically connected to the second electrode, the source line, and the word line.

11. The non-volatile memory device of claim 8 , further comprising an anti-ferromagnetic layer disposed between the fixed magnetic layer and the first electrode.

12. The non-volatile memory device of claim 8 , wherein only the fixed magnetic layer comprises a half-metal material at the interface with the dielectric layer.

13. The non-volatile memory device of claim 12 , wherein the fixed magnetic layer further comprises a ferroelectric material disposed between the half-metal material and the first electrode, distal from the interface of the fixed magnetic layer with the dielectric layer.

14. The non-volatile memory device of claim 12 , wherein the free magnetic layer comprises a ferroelectric material.

15. The non-volatile memory device of claim 14 , wherein the free magnetic layer further comprises a half-metal material disposed between the ferroelectric material and the second electrode, distal from the interface of the free magnetic layer with the dielectric layer.

16. The non-volatile memory device of claim 8 , wherein the half-metal material is a ferromagnetic metal alloy based on a Heusler phase.

17. A magnetic tunneling junction, comprising:
a free magnetic layer;
a fixed magnetic layer; and
a dielectric layer disposed between the free magnetic layer and the fixed magnetic layer, wherein one or both of the free magnetic layer and the fixed magnetic layer comprises a half-metal material at an interface with the dielectric layer, and wherein the half-metal material comprises Fe 3 Si.

18. The magnetic tunneling junction of claim 17 , wherein only the fixed magnetic layer comprises a half-metal material at the interface with the dielectric layer.

19. The magnetic tunneling junction of claim 18 , wherein the fixed magnetic layer further comprises a ferroelectric material adjacent the half-metal material, distal from the interface of the fixed magnetic layer with the dielectric layer.

20. The magnetic tunneling junction of claim 18 , wherein the free magnetic layer comprises a ferroelectric material.

21. The magnetic tunneling junction of claim 20 , wherein the free magnetic layer further comprises a half-metal material adjacent the ferroelectric material, distal from the interface of the free magnetic layer with the dielectric layer.

22. The magnetic tunneling junction of claim 17 , wherein the half-metal material is a ferromagnetic metal alloy based on a Heusler phase.

23. The magnetic tunneling junction of claim 17 , further comprising
an anti-ferromagnetic layer adjacent the fixed magnetic layer, distal from the interface of the fixed magnetic layer with the dielectric layer.

Assignees

• Kuo Charles C
• Mojarad Roksana Golizadeh
• Doyle Brian S
• Kencke David L
• Oguz Kaan
• Chau Robert S
• Intel Corp

Inventors

• Kuo Charles C
• Mojarad Roksana Golizadeh
• Doyle Brian S
• Kencke David L
• Oguz Kaan
• Chau Robert S

Classifications

• H01L43/08

  Electricity · mapped topic

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• H01L29/82

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic