Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability

Patent metadata

Field	Value
Publication number	US-9727685-B2
Application number	US-201514712830-A
Country	US
Kind code	B2
Filing date	May 14, 2015
Priority date	May 14, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value.

First claim

What is claimed is:

1. A method for providing a layout for an integrated circuit device, comprising:
receiving a design for an integrated circuit device, wherein said design comprises a functional cell comprising a boundary;
providing a first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of said functional cell, said first substitute functional cell comprising at least one pin moved by an amount of said first value;
determining whether a shift amount of said set of routing tracks corresponds to said first value;
replacing said functional cell with said first substitute functional cell in response to a determination that said shift amount of said set of routing tracks corresponds to said first value; and
fabricating said integrated circuit based upon said layout.

2. The method of claim 1 , further comprising
providing a second substitute functional cell for a second value of shift of said set of routing tracks respective to the boundary of said functional cell, said second substitute functional cell comprising at least one pin moved by an amount of said second value;
determining whether said shift amount of said set of routing tracks corresponds to at least one of said first value or said second value; and
replacing said functional cell with said first substitute functional cell in response to a determination that said shift amount of said set of routing tracks corresponds to said first value, or replacing said functional cell with said second substitute functional cell in response to a determination that said shift amount of said set of routing tracks corresponds to said second value.

3. The method of claim 2 , wherein determining said shift amount comprises determining an amount of post placement shift.

4. The method of claim 1 , wherein receiving a design for an integrated circuit device, wherein said design comprises a functional cell comprise receiving a 10 nm design comprising a functional cell having at least one 10 nm component.

5. The method of claim 1 , wherein providing a first substitute functional cell for a first value of shift comprises providing said first substitute functional cell for a 32 nm shift of said tracking route.

6. The method of claim 1 , wherein providing a first substitute functional cell for a first value of shift comprises providing said first substitute functional cell for a 16 nm shift of said tracking route.

7. The method of claim 1 , wherein providing said first substitute functional cell for a first value of shift of a set of routing tracks comprises providing said first substitute functional cell for said first value of shift of a set of vertical routing tracks.

8. The method of claim 7 , wherein providing said first substitute functional cell for said first value of shift of said set of vertical routing tracks comprises providing said first substitute functional cell for said first value of shift of an M 3 metal layer routing track.

9. The method of claim 7 , wherein providing said first substitute functional cell comprising at least one pin moved by said amount of said first value comprises providing said first substitute functional cell comprising at least one horizontal pin moved by an amount of said first value.

10. The method of claim 9 , wherein providing said first substitute functional cell comprising at least one horizontal pin moved by an amount of said first value comprises providing said first substitute functional cell comprising at least one M 2 metal layer horizontal pin moved by said amount of said first value.

11. A method for providing a layout for an integrated circuit device, comprising:
placing a functional cell for a design of an integrated circuit device, wherein said functional cell is enclosed within a boundary;
determining a first shift value of a set of vertical metal layer routing tracks relative to the boundary of the functional cell;
providing a first substitute functional cell corresponding to said first shift value, wherein said first predetermined substitute functional cell comprises at least one horizontal feature of a metal layer comprising vertical routing tracks shifted by an amount of the first shift value;
determining whether a shift amount of said set of vertical metal layer routing tracks corresponds to said first shift value;
substituting said functional cell with said first predetermined substitute functional cell in response to a determination that said shift amount of said set of vertical metal layer routing tracks corresponds to said first shift value; and
fabricating said integrated circuit based upon said layout.

12. The method of claim 11 , further comprising:
determining a second shift value of said set of vertical metal layer routing tracks relative to the boundary of the functional cell;
providing a second substitute functional cell corresponding to said second shift value, said second substitute functional cell comprising at least one horizontal feature moved by an amount of said second shift value;
determining whether said shift amount of said set of vertical metal layer routing tracks corresponds to at least one of said first shift value or said second shift value; and
replacing said functional cell with said first substitute functional cell in response to a determination that said shift amount of said set of vertical metal layer routing tracks corresponds to said first value, or replacing said functional cell with said second substitute functional cell in response to a determination that said shift amount of said set of vertical metal layer routing tracks corresponds to said second shift value.

13. The method of claim 11 , wherein:
determining said first shift value of a set of vertical metal layer routing tracks relative to the boundary of the functional cell comprises determining said first shift value of a set of vertical M 3 metal layer routing tracks relative to the boundary of the functional cell; and
providing said first substitute functional cell comprising at least one horizontal feature of a metal layer comprising vertical routing tracks comprises providing said first substitute functional cell comprising at least one horizontal feature of an M 2 metal layer comprising vertical routing tracks.

14. A system, comprising:
a design unit adapted to:
receive a design for an integrated circuit device, wherein said design comprises a functional cell within a boundary;
provide a first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of said functional cell, said first substitute functional cell comprising at least one feature moved by an amount of said first value;
determine whether a shift amount of said set of routing tracks corresponds to said first value; and
replace said functional cell with said first substitute functional cell in response to a determination that said shift amount corresponds to said first value;

a semiconductor device processing system for fabricating an integrated circuit device based upon said circuit layout; and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system.

15. The system of claim 14 , wherein:
said set of routing tracks are a set of vertical M 3 layer routing tracks; and
said feature is a horizontal feature in an M 2 metal layer.

16. The system of claim 14 , wherein said design unit is further configured to
provide a second substitute functional cell for a second

Assignees

• Globalfoundries Inc

Inventors

• Yuan Lei
• Wang Yan
• Wang Chenchen
• Kye Jongwook

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5072

  Physics · mapped topic

• G06F17/5077

  Physics · mapped topic