Integrated circuits with universal serial bus 2.0 and embedded universal serial bus 2 connectivity

Patent metadata

Field	Value
Publication number	US-9727514-B2
Application number	US-201514590780-A
Country	US
Kind code	B2
Filing date	Jan 6, 2015
Priority date	Dec 9, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line, the communication-mode determination circuitry configured to determine whether a communication mode of the first data line and the second data line is a first universal serial bus (USB) communication mode or a second USB communication mode;
a first transceiver circuitry configured to operate in one of a first plurality of modes, based on the communication mode determined; and
a second transceiver circuitry configured to operate in one of a second plurality of modes, based on the communication mode determined, wherein at least one of the second plurality of modes is associated with a higher maximum signal level than each of the first plurality of modes,
wherein a maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode, and wherein the second plurality of modes comprises a second speed mode of the first USB communication mode and a third speed mode of the first USB communication mode.

2. The integrated circuit of claim 1 ,
wherein the first plurality of modes comprises a first speed mode of the first USB communication mode and a first speed mode of the second USB communication mode.

3. The integrated circuit of claim 2 , wherein the first plurality of modes further comprises a second speed mode of the second USB communication mode and a third speed mode of the second USB communication mode.

4. The integrated circuit of claim 1 ,
wherein a first predetermined threshold voltage is less than the maximum signal level of the first USB communication mode,
wherein the first predetermined threshold voltage is greater than the maximum signal level of the second USB communication mode,
wherein when the detected signal level is greater than the first predetermined threshold voltage, the communication-mode determination circuitry is configured to determine that the communication mode of the first data line and the second data line is the first USB communication mode, and
wherein when the detected signal level is less than the first predetermined threshold voltage, the communication-mode determination circuitry is configured to determine that the communication mode of the first data line and the second data line is the second USB communication mode.

5. The integrated circuit of claim 1 , wherein the first transceiver circuitry comprises a voltage protection circuitry configured to protect circuitry in the first transceiver circuitry from a voltage level associated with the second transceiver circuitry.

6. The integrated circuit of claim 5 , wherein the voltage protection circuitry is coupled to the first data line and the second data line.

7. The integrated circuit of claim 5 , wherein the first transceiver circuitry comprises:
a first driver circuitry associated with a first speed mode of the first USB communication mode and a first speed mode of the second USB communication mode, and
a second driver circuitry associated with a second speed mode of the second USB communication mode and a third speed mode of the second USB communication mode,
wherein the voltage protection circuitry is coupled to the first driver circuitry and the second driver circuitry.

8. The integrated circuit of claim 7 , wherein the first driver circuitry is configured to transmit at least two signals, the first transceiver circuitry further comprising:
a first transistor configured to receive one of the at least two signals, and
a second transistor configured to receive one of the at least two signals,
wherein the first transistor and the second transistor are coupled to the voltage protection circuitry.

9. The integrated circuit of claim 5 , wherein the voltage protection circuitry comprises at least one laterally diffused metal-oxide semiconductor transistor.

10. The integrated circuit of claim 1 , wherein the first USB communication mode is a USB 2.0 communication mode, and the second USB communication mode is an embedded USB2 communication mode.

11. The integrated circuit of claim 1 , wherein the integrated circuit is configured to establish a connection with a connecting component, the integrated circuit configured to determine a speed mode associated with the connecting component based at least on the connection.

12. An integrated circuit, comprising:
a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line, the communication-mode determination circuitry configured to determine a communication mode of the first data line and the second data line, wherein the communication mode is one of a first universal serial bus (USB) communication mode or a second USB communication mode;
a first shared transceiver circuitry configured to operate in one of a first plurality of modes of the first USB communication mode or the second USB communication mode, based on the communication mode determined;
a second shared transceiver circuitry configured to operate in one of a second plurality of modes of the first USB communication mode, based on the communication mode determined; and
a voltage protection circuitry configured to protect circuitry in the first shared transceiver circuitry from a voltage level associated with the second shared transceiver circuitry,
wherein a maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.

13. The integrated circuit of claim 12 ,
wherein the first plurality of modes comprises a first speed mode of the first USB communication mode, a first speed mode of the second USB communication mode, a second speed mode of the second USB communication mode, and a third speed mode of the second USB communication mode, and
wherein the second plurality of modes comprises a second speed mode of the first USB communication mode and a third speed mode of the first USB communication mode.

14. The integrated circuit of claim 12 ,
wherein a first predetermined threshold voltage is less than the maximum signal level of the first USB communication mode,
wherein the first predetermined threshold voltage is greater than the maximum signal level of the second USB communication mode,
wherein when the detected signal level is greater than the first predetermined threshold voltage, the communication-mode determination circuitry is configured to determine that the communication mode of the first data line and the second data line is the first USB communication mode, and
wherein when the detected signal level is less than the first predetermined threshold voltage, the communication-mode determination circuitry is configured to determine that the communication mode of the first data line and the second data line is the second USB communication mode.

15. The integrated circuit of claim 12 , wherein the first shared transceiver circuitry comprises a variable resistance termination, a resistance of the variable resistance termination being based on whether the communication mode is the first USB communication mode or the second USB communication mode and whether a speed mode is a first speed mode, second speed mode, or third speed mode.

16. The integrated circuit of claim 12 , wherein the first shared transceiver circuitry comprises:
a first driver circuitry associated with a first speed mode of the first USB communication mode and a first speed mode of the second USB communication mode, and

Assignees

• Broadcom Corp
• Avago Technologies General Ip

Inventors

• Ma Desheng
• Tam Derek Hing Sang
• Hsu Chia-Jen
• Mulage Preeti

Classifications

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• G06F13/4059 Primary

  where the synchronisation uses buffers, e.g. for speed matching between buses · CPC title