Resolving multi-core shared cache access conflicts

Patent metadata

Field	Value
Publication number	US-9727468-B2
Application number	US-4552505-A
Country	US
Kind code	B2
Filing date	Jan 28, 2005
Priority date	Sep 9, 2004
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

First claim

What is claimed is:

1. An integrated circuit comprising:
a plurality of processing cores coupled to a shared inclusive cache to store information contained within each of a plurality of local caches corresponding to the plurality of processing cores; and
circuitry to save, in a storage external to the shared inclusive cache, coherency state information of a cache line stored in the shared inclusive cache on detection of a miss for a read request from a requestor to the cache line in a local cache of one of the plurality of processing cores that is to cause an access to the cache line in the shared inclusive cache, invalidate the cache line stored in the shared inclusive cache when the read request is to cause a cross snoop, and fill the cache line and refill, from the storage, the coherency state information of the cache line into the shared inclusive cache after the cache line is delivered to the requestor.

2. The integrated circuit of claim 1 , wherein a cache line fill to the cache line is to cause an eviction of the cache line from the shared inclusive cache.

3. The integrated circuit of claim 1 , wherein the coherency state information includes at least one bit to indicate that the cache line is atomically invalidated in the shared inclusive cache as a result of the access.

4. The integrated circuit of claim 1 , wherein the storage is a register, and the circuitry is to save the coherency state information of the cache line stored in the shared inclusive cache into the register within the circuitry.

5. The integrated circuit of claim 1 , wherein the circuitry is to invalidate the cache line stored in the shared inclusive cache when the read request is to cause a cross snoop and no cancellation signal is detected by the circuitry.

6. The integrated circuit of claim 1 , wherein the shared inclusive cache is a last level cache (LLC).

Assignees

• Sistla Krishnakanth V
• Liu Yen-Cheng
• Cai George
• Gilbert Jeffrey D
• Intel Corp

Inventors

• Sistla Krishnakanth V
• Liu Yen-Cheng
• Cai George
• Gilbert Jeffrey D

Classifications

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title