Interconnect and method of managing a snoop filter for an interconnect

Patent metadata

Field	Value
Publication number	US-9727466-B2
Application number	US-201514822953-A
Country	US
Kind code	B2
Filing date	Aug 11, 2015
Priority date	Aug 26, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage. The coherency control circuitry then responds to the snoop control data by issuing a snoop transaction to each master device indicated by the snoop control data, in order to cause a snoop operation to be performed in their associated cache storage in order to generate snoop response data. Analysis circuitry then determines from the snoop response data an update condition, and upon detection of the update condition triggers performance of an update operation within the snoop filter circuitry to update the address-dependent caching indication data. By subjecting the snoop response data to such an analysis, it is possible to identify situations where the caching indication data has become out of date, and update that caching indication data accordingly, this giving rise to significant performance benefits in the operation of the interconnect.

First claim

The invention claimed is:

1. An interconnect for connecting devices, the devices including a plurality of master devices, one or more of the master devices having associated cache storage, the interconnect comprising:
coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices;
snoop filter circuitry to maintain address-dependent caching indication data and, responsive to a data access transaction specifying a target address, to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage;
the coherency control circuitry being responsive to said snoop control data to issue a snoop transaction to each master device indicated by the snoop control data, in order to cause a snoop operation to be performed in their associated cache storage in order to generate snoop response data; and
analysis circuitry to determine from the snoop response data an update condition where there is an inconsistency between the snoop response data and the snoop control data, and upon detection of said update condition to trigger performance of an update operation within the snoop filter circuitry to update the address-dependent caching indication data to remove said inconsistency.

2. An interconnect as claimed in claim 1 , wherein the snoop filter circuitry is arranged to maintain the address-dependent caching indication data in response to cache allocation information and cache eviction information issued by the plurality of master devices.

3. An interconnect as claimed in claim 2 , wherein at least one of the master devices is arranged to perform at least one type of cache eviction operation in respect of its associated cache storage without passing corresponding cache eviction information to the coherency control circuitry.

4. An interconnect as claimed in claim 1 , wherein the snoop filter circuitry comprises a snoop filter storage having a plurality of entries, each entry arranged to store an address identifier and the caching indication data for that address identifier.

5. An interconnect as claimed in claim 4 , wherein:
the analysis circuitry is arranged to determine the update condition by detecting a situation where the snoop response data identifies that the associated cache storage of at least one master device no longer stores cached data for the target address, and the snoop control data for that target address indicates that said at least one master device did store the cached data; and
the snoop filter circuitry is arranged to perform the update operation triggered by the update condition in order to update the address-dependent caching indication data for the entry whose address identifier corresponds to the target address.

6. An interconnect as claimed in claim 5 , wherein when the snoop response data identifies that the cached data for the target address is no longer stored in the associated cache storage of any of said master devices, the snoop circuitry is arranged to perform the update operation in order to invalidate the corresponding entry in the snoop filter storage.

7. An interconnect as claimed in claim 5 , wherein the analysis circuitry is arranged to detect the update condition by comparing a first vector derived from the snoop control data with a second vector derived from the snoop response data, both the first and second vectors having a field for each of the master devices, with each field being set or unset dependent on whether the snoop control data or snoop response data identifies the associated master device as storing the cached data in its associated cache storage.

8. An interconnect as claimed in claim 7 , wherein:
the caching indication data in each entry of the snoop filter storage takes the form of a snoop vector identifying for each master device whether that master device has cached data associated with that address identifier; and
the snoop filter circuitry is arranged, on detection of the update condition in a situation where the second vector identifies at least one master device as still storing the cached data for the target address, to perform the update operation in order to update the snoop vector for the entry whose address identifier corresponds to the target address to match the second vector.

9. An interconnect as claimed in claim 4 , wherein in each entry of the snoop filter storage the caching indication data includes a master identifier field identifying a master device, and a multiple field identifying whether one master device or multiple master devices store the cached data.

10. An interconnect as claimed in claim 9 , wherein:
when the entry associated with the target address has the multiple field set the coherency control circuitry is arranged to issue the snoop transaction to all of the master devices;
the analysis circuitry is arranged to detect the update condition when the snoop response data indicates that only one master device still stores the cached data in its associated cache storage; and
the snoop filter circuitry is responsive to the update condition to unset the multiple field in the corresponding entry of the snoop filter to identify that one master device stores the cached data and to update the master identifier field to identify the one master device indicated by the snoop response data as still storing the cached data.

11. An interconnect as claimed in claim 10 , wherein when the entry associated with the target address has the multiple field unset the coherency control circuitry is arranged to issue the snoop transaction to the master device identified in the master identifier field.

12. An interconnect as claimed in claim 4 , wherein the address identifier identifies a unique address, and the caching indication data indicates which master devices have cached data for that unique address.

13. An interconnect as claimed in claim 4 , wherein the address identifier identifies an address range, and the caching indication data indicates which master devices have cached data within that address range.

14. An interconnect as claimed in claim 4 , wherein
the address identifier identifies an address range; and
the caching indication data provides a counter value for each master device indicating the number of allocations into the associated cache structure of cached data within that address range.

15. An interconnect as claimed in claim 14 , wherein the snoop filter circuitry is arranged to adjust in a first direction the counter value for a master device each time the coherency control circuitry is advised that that master device has made a further allocation of cached data within that address range into its associated cache structure, and to adjust in a second direction the counter value for a master device each time the coherency control circuitry is advised that that master device has performed an eviction of cached data within that address range from its associated cache structure.

16. An interconnect as claimed in claim 14 , wherein:
the snoop response data provides a further counter value for each master device identifying a number of cached entries in the associated cache storage currently storing cached data within the address range; and
the analysis circuitry is arranged to determine the update condition by detecting a situation where, for at least one of the master devices, the further counter value provided by the snoop response data differs from the counter value provided by the caching indication data.

17. An interconnect as claimed i

Assignees

• Advanced Risc Mach Ltd

Inventors

• Tune Andrew David
• Salisbury Sean James

Classifications

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic