Translating an address associated with a command communicated between a system and memory circuits

Patent metadata

Field	Value
Publication number	US-9727458-B2
Application number	US-201213620650-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Feb 9, 2006
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

First claim

What is claimed is:

1. An apparatus comprising:
an interface circuit electrically connected to a first number of physical dynamic random access memory (“DRAM”) devices via multiple data paths including a first data path and a distinct second data path, wherein each of the physical DRAM devices is an individual and independent monolithic device, the interface circuit configured to:
communicate with the first number of physical DRAM devices and a memory controller,
interface the first number of physical DRAM devices to simulate a different, second number of virtual DRAM devices as presented to the memory controller, each of the virtual DRAM devices being simulated as an individual and independent monolithic device,
simulate a first virtual DRAM device using a first physical DRAM device on the first data path and a second physical DRAM device on the distinct second data path,
use both a physical row of the first physical DRAM device and a physical row of the second physical DRAM device to simulate a virtual row of the first virtual DRAM device,
receive a row-access command from the memory controller, directed to the first virtual DRAM device, for the virtual row of the first virtual DRAM device,
based on the received row-access command, translate the received row-access command for the virtual row to a first row access command for the physical row of the first physical DRAM device and a second row access command for the physical row of the second physical DRAM device, and
issue the first row access command and the second row access command to activate the physical row of the first physical DRAM device and the physical row of the second physical DRAM device, respectively, before a subsequent column-access command is received from the memory controller to access a part of the simulated row that corresponds to the physical row of the first physical DRAM device or the physical row of the second physical DRAM device.

2. The apparatus of claim 1 , wherein the virtual row has a virtual row size and each of the physical rows has a physical row size, and the virtual row size is greater than the physical row size.

3. The apparatus of claim 1 , wherein the first number of physical DRAM devices are associated with first command scheduling constraints and the different, second number of virtual DRAM devices are associated with second command scheduling constraints different from the first command scheduling constraints; and
the interface circuit is further configured to interface the first number of physical DRAM devices to the memory controller such that the first command scheduling constraints are met.

4. The apparatus of claim 3 , wherein the first command scheduling constraints and the second command scheduling constraints include intra-device command scheduling constraints.

5. The apparatus of claim 4 , wherein the intra-device command scheduling constraints include at least one of a column to column delay time (tCCD), a row to row activation delay time (tRRD), a four-bank activation window time (tFAW), or a write-to-read turn-around time (tWTR).

6. The apparatus of claim 3 , wherein the first command scheduling constraints and the second command scheduling constraints include inter-device command scheduling constraints.

7. The apparatus of claim 6 , wherein the inter-device command scheduling constraints include at least one of a rank to rank data bus turnaround time or an on die termination (ODT) control switching time.

8. The apparatus of claim 1 , wherein the interface circuit is a circuit separate from the physical DRAM devices and is positioned on a dual inline memory module (DIMM) with the physical DRAM devices.

9. The apparatus of claim 1 , wherein each of the first number of physical DRAM devices comprises a respective plurality of physical memory banks, and wherein each of the second number of virtual DRAM devices comprises two or more physical memory banks of at least two physical DRAM devices of the first number of physical DRAM devices.

10. A system comprising:
a first number of physical dynamic random access memory (“DRAM”) devices;
an interface circuit electrically connected to the first number of physical DRAM devices via multiple data paths including a first data path and a distinct second data path, wherein each of the physical DRAM devices is an individual and independent monolithic device, the interface circuit configured to:
communicate with the first number of physical DRAM devices and a memory controller,
interface the first number of physical DRAM devices to simulate a different, second number of virtual DRAM devices as presented to the memory controller, each of the virtual DRAM devices being simulated as an individual and independent monolithic device,
simulate a first virtual DRAM device using a first physical DRAM device on the first data path and a second physical DRAM device on the distinct second data path,
use both a physical row of the first physical DRAM device and a physical row of the second physical DRAM device to simulate a virtual row of the first virtual DRAM device,
receive a row-access command from the memory controller, directed to the first virtual DRAM device, for the virtual row of the first virtual DRAM device,
based on the received row-access command, translate the received row-access command for the virtual row to a first row access command for the physical row of the first physical DRAM device and a second row access command for the physical row of the second physical DRAM device, and
issue the first row access command and the second row access command to activate the physical row of the first physical DRAM device and the physical row of the second physical DRAM device, respectively, before a subsequent column-access command is received from the memory controller to access a part of the simulated row that corresponds to the physical row of the first physical DRAM device or the physical row of the second physical DRAM device.

11. The system of claim 10 , wherein the virtual row has a virtual row size and each of the physical rows has a physical row size, and the virtual row size is greater than the physical row size.

12. The system of claim 10 , wherein the first number of physical DRAM devices are associated with first command scheduling constraints and the different, second number of virtual DRAM devices are associated with second command scheduling constraints different from the first command scheduling constraints; and
the interface circuit is further configured to interface the first number of physical DRAM devices to the memory controller such that the first command scheduling constraints are met.

13. The system of claim 12 , wherein the first command scheduling constraints and the second command scheduling constraints include intra-device command scheduling constraints.

14. The system of claim 12 , wherein the first command scheduling constraints and the second command scheduling constraints include inter-device command scheduling constraints.

15. The system of claim 10 , wherein each of the first number of physical DRAM devices comprises a respective plurality of physical memory banks, and wherein each of the second number of virtual DRAM devices comprises two or more physical memory banks of at least two physical DRAM devices of the first number of physical DRAM devices.

16. A method, comprising:
communicating with a first number of physical dynamic random access memory (“DRAM”) devices and a memory controller, wherein each of the physical DRAM devices is an individual and independent monolithic device;
interfacing the first number of ph

Assignees

• Wang David T
• Rajan Suresh Natarajan
• Schakel Keith R
• Smith Michael John Sebastian
• Weber Frederick Daniel
• Google Inc

Inventors

• Wang David T
• Rajan Suresh Natarajan
• Schakel Keith R
• Smith Michael John Sebastian
• Weber Frederick Daniel

Classifications

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G06F13/4243

  with synchronous protocol · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title