Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers

Patent metadata

Field	Value
Publication number	US-9727337-B2
Application number	US-201213681520-A
Country	US
Kind code	B2
Filing date	Nov 20, 2012
Priority date	Sep 16, 2011
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).

First claim

What is claimed is:

1. A method comprising:
obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising:
at least one opcode field identifying the machine instruction, execution of which is to access one or more registers of a register file; and
at least one field used to distinguish between subranges of registers of the register file, wherein the subranges of registers of the register file comprise subranges of multiple consecutive registers; and

executing, by the processor, the machine instruction, the executing comprising:
obtaining, based on the machine instruction, a value indicating one subrange of registers of the subranges of registers of the register file;
determining that the value indicates the one subrange of registers;
based on the indicated one subrange of registers, checking a corresponding at least one control indicator, of a plurality of control indicators for controlling enablement of a plurality of operations, the corresponding at least one control indicator indicating whether or not an operation, of the plurality of operations, indicated by the at least one opcode field is enabled to be performed, the operation to access the indicated one subrange of registers, wherein the corresponding at least one control indicator controls enablement of the operation separate from and regardless of enablement of one or more other operations of the plurality of operations; and
performing the operation using the indicated one subrange of registers, based on the checking indicating that the operation is enabled to be performed.

2. The method of claim 1 , wherein the subranges of registers comprise a floating point subrange of multiple consecutive registers and a vector subrange of multiple consecutive registers.

3. The method of claim 1 , wherein the corresponding at least one control indicator comprises a floating point enable indicator or a vector enable indicator depending on the value obtained based on the machine instruction.

4. The method of claim 1 , wherein the corresponding at least one control indicator comprises a floating point enable indicator, a vector enable indicator or a vector-scalar enable indicator.

5. The method of claim 1 , wherein the operation is a sub-function of a function, the sub-function defined by the indicated one subrange of registers indicated by the value.

6. The method of claim 5 , wherein the sub-function is a move-floating point sub-function or a move-vector sub-function, depending on the indicated one subrange of registers.

7. The method of claim 1 , wherein the corresponding at least one control indicator is located within a register, the register comprising the plurality of control indicators, said plurality of control indicators comprising an enable indicator for the indicated one subrange of registers and an enable indicator for another subrange of registers of the subranges of registers.

8. The method of claim 1 , wherein the indicated one subrange of registers comprises a first 32 registers of the register file and another subrange of registers of the subranges of registers comprises a next 32 registers of the register file.

9. The method of claim 1 , wherein the indicated one subrange of registers comprises a last 32 registers of the register file and another subrange of registers of the subranges of registers comprises a first 32 registers of the register file.

10. The method of claim 1 , wherein the executing further comprises taking an interrupt, based on the checking indicating that the operation is not enabled to be performed.

Assignees

• IBM

Inventors

• Gschwind Michael K
• Olsson Brett
• Salapura Valentina

Classifications

• G06F9/30025

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title

• G06F9/30105

  Register structure · CPC title

• G06F9/30098 Primary

  Register arrangements · CPC title