Selection of an open block in solid state storage systems with multiple open blocks

Patent metadata

Field	Value
Publication number	US-9727249-B1
Application number	US-201414543333-A
Country	US
Kind code	B1
Filing date	Nov 17, 2014
Priority date	Feb 6, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

An instruction to write data to a write logical address is received where the write logical address is a member of a group of one or more logical addresses. It is determined if data associated with any of the logical addresses in the group of logical addresses has been written to any of a plurality of open groups of locations. If so, the data is written to the open group of locations to which data from the group of logical addresses has already been written to. If not, an open group of locations to write to is selected from the plurality of open groups of locations.

First claim

What is claimed is:

1. A system, comprising:
a host interface configured to receive an instruction for writing write data to a write logical address, wherein the write logical address is a member of a first logical address group wherein the first logical address group is one of a plurality of logical address groups comprising a plurality of logical addresses;
a block selector configured for selecting an open block from a plurality of open blocks for writing the write data, wherein each of the plurality of open blocks comprises a group of physical addresses having at least one of the physical addresses thereof valid for writing the write data, and wherein the selecting the open block includes:
determining if any existing data, whose associated logical address is in the first logical address group, has been previously written to a first open block, wherein the first open block is one of the plurality of open blocks;
in the event it is determined that the any existing data whose associated logical address is in the first logical address group has been previously written to the first open block, selecting the first open block to which to write the write data;
in the event it is determined that the any existing data whose associated logical address is in the first logical address group has not been previously written to the first open block, selecting one of the plurality of open blocks to which to write the write data; and
writing the write data to the selected open block.

2. The system recited in claim 1 , further comprising solid state storage and a storage interface, wherein the storage interface is configured to write to the solid state storage.

3. The system recited in claim 1 , wherein the system includes a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

4. The system recited in claim 1 , wherein the block selector is configured to determine, including by:
accessing, in a destination table, an entry associated with the write logical address; and
determining if a destination field in the entry indicates that data associated with the group of logical addresses has been previously written to the first open block.

5. The system recited in claim 1 , wherein the block selector is configured to determine, including by:
determining a physical address that corresponds to the logical address using a LBA table;
obtaining a block number from the physical address; and
determining if the block corresponding to the block number is still open.

6. The system recited in claim 1 , wherein the block selector is configured to select based at least in part on a traffic classification.

7. The system recited in claim 6 , wherein a single-level cell (SLC) open block is selected in the event the traffic classification is associated with a short, random write and a multi-level cell (MLC) open block is selected in the event the traffic classification is associated with a long, sequential write.

8. The system recited in claim 6 , wherein an open block from a first group of blocks is selected in the event the traffic classification is associated with hot data and an open block from a second group of blocks is selected in the event the traffic classification is associated with cold data.

9. The system recited in claim 6 , wherein the traffic classification is provided by a host.

10. The system recited in claim 6 , wherein the block selector is further configured to generate the traffic classification.

11. A method, comprising:
receiving an instruction for writing write data to a write logical address, wherein the write logical address is a member of a first logical address group, wherein the first logical address group is one of a plurality of logical address groups comprising a plurality of logical addresses;
using a processor to determine if any existing data, whose associated logical address is in the first logical address group, has been previously written to a first open block, wherein the first open block is one of a plurality of open blocks, each of the plurality of open blocks comprises a group of physical addresses having at least one of the physical addresses thereof valid for writing the write data;
in the event it is determined that the any existing data whose associated logical address is in the first logical address group has been previously written to the first open block, selecting the first open block to which to write the write data;
in the event it is determined that the any existing data whose associated logical address is in the first logical address group has not been previously written to the first open block, selecting one of the plurality of open blocks to which to write the write data; and
writing the write data to the selected open block.

12. The method recited in claim 11 , wherein the method is performed by a semiconductor device, including one or more of the following: an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).

13. The method recited in claim 11 , wherein using a processor to determine includes:
accessing, in a destination table, an entry associated with the write logical address; and
determining if a destination field in the entry indicates that data associated with the group of logical addresses has been previously written to the first open block.

14. The method recited in claim 11 , wherein using a processor to determine includes:
determining a physical address that corresponds to the logical address using a LBA table;
obtaining a block number from the physical address; and
determining if the block corresponding to the block number is still open.

15. The method recited in claim 11 , wherein selecting is based at least in part on a traffic classification.

16. The method recited in claim 15 , wherein a single-level cell (SLC) open block is selected in the event the traffic classification is associated with a short, random write and a multi-level cell (MLC) open block is selected in the event the traffic classification is associated with a long, sequential write.

17. The method recited in claim 15 , wherein an open block from a first group of blocks is selected in the event the traffic classification is associated with hot data and an open block from a second group of blocks is selected in the event the traffic classification is associated with cold data.

18. The method recited in claim 15 , wherein the traffic classification is provided by a host.

19. A computer program product, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
receiving an instruction for writing write data to a write logical address, wherein the write logical address is a member of a first logical address group, wherein the first logical address group is one of a plurality of logical address groups comprising a plurality of logical addresses;
determining if any existing data, whose associated logical address is in the first logical address group, has been previously written to a first open block, wherein the first open block is one of a plurality of open blocks, each of the plurality of open blocks comprises a group of physical addresses having at least one of the physical addresses thereof valid for writing the write data;
in the event it is determined that the any existing data whose associated logical address is in the first logical address group has been previously written to the first open block,

Assignees

• Sk Hynix Inc

Inventors

• Subramanian Arunkumar
• Wu Zheng
• Indupuru Suneel Kumar
• Bellorado Jason

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F2212/2022

  Flash memory · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title