Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth

Patent metadata

Field	Value
Publication number	US-9726819-B2
Application number	US-201615363471-A
Country	US
Kind code	B2
Filing date	Nov 29, 2016
Priority date	Oct 8, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.

First claim

What is claimed is:

1. An electrical device comprising:
an optical interconnect positioned on a portion of the semiconductor substrate that is positioned between portions of a semiconductor substrate including electrical components, the optical interconnect is present on at least one interlevel dielectric layer that is present over at least one of the electrical components, the optical interconnect including a III-V light emission device and a III-V light detection device, wherein at least one material layer of the optical interconnect is an epitaxial material that is in direct contact with a semiconductor material layer of the substrate that is overlying a dielectric layer.

2. The electrical device of claim 1 , wherein the semiconductor substrate is an SOI substrate.

3. The electronic device of claim 1 further comprising a dielectric waveguide positioned between the III-V light emission device and the III-V light detection device.

4. The electronic device of claim 1 , wherein the electronic components comprises a switching device selected from the group consisting of field effect transistor (FET), fin field effect transistor (FinFET), metal oxide semiconductor field effect transistor (MOSFET), bipolar junction transistor (BJT), Schottky barrier semiconductor device, junction field effect transistor (JFET) and combinations thereof, or the first electronic component comprises a memory device selected from the group consisting of flash memory, dynamic random access memory, embedded dynamic random access memory, and combinations thereof.

5. The electronic device of claim 1 , wherein the III-V light emission device is a quantum well laser comprising a first conductivity type III-V semiconductor material layer, a quantum well stack of III-V semiconductor material layers that is present on the first conductivity type III-V semiconductor material layer, and a second conductivity type III-V semiconductor material layer that is present on the quantum well stack of III-V semiconductor material layers.

6. The electronic device of claim 1 , wherein the III-V light detection device includes a first conductivity type III-V semiconductor material layer, an intrinsic III-V semiconductor material layer, and a second conductivity type III-V semiconductor material layer.

7. The electronic device of claim 1 , wherein the first electronic component is in electrical communication through at least one first interconnect to the III-V light emission device of the optical interconnect, and the second electronic component is in electrical communication through at least one second interconnect to the III-V light detection device of the optical interconnect.

8. The electrical device of claim 2 , wherein the dielectric waveguide has a width that tapers from a first face having a first width that is adjacent to the III-V light emission device to a second face having a second width that is adjacent to the III-V light detection device.

9. The electrical device of claim 8 , wherein the dielectric waveguide is comprised of a dielectric material selected from the group consisting of amorphous silicon, polysilicon, poly III-V semiconductor material, aluminum nitride (AlN) and a combination thereof.

10. An electrical device comprising:
an optical interconnect positioned on the interlevel dielectric and in communication with a semiconductor device, the optical interconnect including, an epitaxial material that is in direct contact with a seed surface of an underlying semiconductor surface through a via extending through the interlevel dielectric layer.

11. The electrical device of claim 10 , wherein the optical interconnect includes a III-V light emitting device, a dielectric waveguide and a III-V light detecting device.

12. The electrical device of claim 10 , wherein the semiconductor device comprises a first switching device selected from the group consisting of field effect transistor (FET), fin field effect transistor (FinFET), metal oxide semiconductor field effect transistor (MOSFET), bipolar junction transistor (BJT), Schottky barrier semiconductor device, junction field effect transistor (JFET) and combinations thereof, or the semiconductor device comprises a first memory device selected from the group consisting of flash memory, dynamic random access memory, embedded dynamic random access memory and combinations thereof.

13. The electrical device of claim 11 , wherein the optoelectronic light emission device is a quantum well laser comprising a first conductivity type III-V semiconductor material layer, a quantum well stack of III-V semiconductor material layers that is present on the first conductivity type III-V semiconductor material layer, and a second conductivity type III-V semiconductor material layer that is present on the quantum well stack of III-V semiconductor material layers.

14. The electrical device of claim 11 , wherein the optoelectronic light detector device comprises a first conductivity type III-V semiconductor layer, an intrinsic III-V semiconductor material layer, and a second conductivity type III-V semiconductor material layer.

15. A method of forming an electrical device comprising:
forming a plurality electrical components; and
forming an optical interconnect on a surface of the at least one interlevel dielectric layer overlying and between at least two adjacent electrical components of said plurality of electrical components, wherein at least one material layer of the optical interconnect is epitaxial grown from a seed surface through at least one via extending onto the upper surface of the at least one interlevel dielectric layer.

16. The method of claim 15 further comprising depositing at least one interlevel dielectric layer over the first, second and third portions of the substrate.

17. The method of claim 16 further comprising etching at least one via through the at least one interlevel dielectric layer to expose the seed substrate surface in the second portion of the substrate.

18. The method of claim 15 , wherein the optical interconnect includes a III-V light emitting device, a dielectric waveguide and a III-V light detecting device.

19. The method of claim 15 , wherein at least one of the III-V light emitting device and the III-V light detecting device is a quantum well laser comprising a first conductivity type III-V semiconductor material layer, a quantum well stack of III-V semiconductor material layers that is present on the first conductivity type III-V semiconductor material layer, and a second conductivity type III-V semiconductor material layer that is present on the quantum well stack of III-V semiconductor material layers.

20. The method of claim 15 , wherein at least one of the III-V light emitting device and the III-V light detecting device comprises a first conductivity type III-V semiconductor layer, an intrinsic III-V semiconductor material layer, and a second conductivity type III-V semiconductor material layer.

Assignees

• IBM

Inventors

• Cheng Cheng-Wei
• Li Ning
• Sadana Devendra K
• Shiu Kuen-Ting

Classifications

• H01L31/173

  Electricity · mapped topic

• H01L31/02322

  Electricity · mapped topic

• H01L31/0232

  Electricity · mapped topic

• G02B6/1228

  Tapered waveguides, e.g. integrated spot-size transformers (for coupling with fibres G02B6/305) · CPC title

• G02B6/12002

  Three-dimensional structures · CPC title