Method and apparatus for low jitter clock recovery in wireless display extensions

Patent metadata

Field	Value
Publication number	US-9723342-B2
Application number	US-201113996621-A
Country	US
Kind code	B2
Filing date	Dec 21, 2011
Priority date	Dec 21, 2011
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

First claim

What is claimed is:

1. A method comprising:
generating with a processor a data packet carrier comprising an optional program clock reference (PCR) value, a variable delay reference (VDR) value, and a validity indicator;
processing with the processor the data packet carrier to determine whether the data packet carrier comprises the optional PCR value;
in response to the data packet carrier not comprising the optional PCR value then generating a surrogate PCR value;
determining with the processor if a media access control retry bit value indicates one of the optional PCR value and the surrogate PCR value is valid;
in response to a validity indication then causing, at least in part, the data packet carrier to be communicated based, at least in part, on the media access control retry bit value;
in response to an invalidity indication then causing, at least in part, one of the optional PCR value and the surrogate PCR value to be discarded;
wherein the surrogate PCR value is generated remotely by a graphics processing unit.

2. A method of claim 1 , further comprising: determining a value of the validity indicator indicates one of the optional PCR value and the surrogate PCR value is valid; causing, at least in part, the value of the validity indicator to change to indicate one of the optional PCR value and the surrogate PCR value is invalid; and causing, at least in part, one of the optional PCR value and the surrogate PCR value to be discarded based, at least in part, on the changed value of the validity indicator.

3. A method of claim 2 , wherein the value of the validity indicator is caused to change by a media access control layer.

4. A method of claim 1 , further comprising: determining a media access control retry bit value indicates one of the optional PCR value and the surrogate PCR value is invalid; causing, at least in part, one of the optional PCR value and the surrogate PCR value to be discarded based, at least in part, on the value of at least the media access control retry bit value.

5. A method of claim 1 , further comprising: determining a value of the validity indicator indicates one of the optional PCR value and the surrogate PCR value is valid.

6. A method of claim 1 , wherein the VDR value is based, at least in part, on one of the optional PCR value and the surrogate PCR value.

7. A method of claim 1 , further comprising: causing, at least in part, a phase-locked loop to lock the surrogate PCR value to a clock of the graphics processing unit.

8. An apparatus comprising:
at least one processor; and
at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following:
generating with the at least one processor a data packet carrier comprising an optional program clock reference (PCR) value, a variable delay reference (VDR) value, and a validity indicator;
process with the at least one processor the data packet carrier to determine whether the data packet carrier comprises the optional PCR value;
in response to the data packet carrier not comprising the optional PCR value then generating a surrogate PCR value;
determine with the at least one processor if a media access control retry bit value indicates one of the optional PCR value and a surrogate PCR value is valid;
in response to a validity indication then cause, at least in part, the data packet carrier to be communicated based, at least in part, on the media access control retry bit value;
in response to an invalidity indication then causing, at least in part, one of the optional PCR value and the surrogate PCR value to be discarded;
cause, at least in part, a phase-locked loop to lock the surrogate PCR value to a clock of a graphics processing unit.

9. An apparatus of claim 8 , wherein the apparatus is further caused to: cause, at least in part, the surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

10. An apparatus of claim 9 , wherein the apparatus is further caused to: determine a value of the validity indicator indicates one of the optional PCR value and the surrogate PCR value is invalid; and cause, at least in part, one of the optional PCR value and the surrogate PCR value to be discarded based, at least in part, on the value of the validity indicator.

11. An apparatus of claim 9 , wherein the apparatus is further caused to: determine a media access control retry bit value indicates one of the optional PCR value and the surrogate PCR value is invalid; cause, at least in part, one of the optional PCR value and the surrogate PCR value to be discarded based, at least in part, on the value of at least the media access control retry bit value.

12. An apparatus of claim 9 , wherein the apparatus is further caused to: determine a media access control retry bit value indicates one of the optional PCR value and the surrogate PCR value is valid; determine a value of the validity indicator indicates one of the optional PCR value and the surrogate PCR value is valid.

13. An apparatus of claim 9 , wherein the VDR value is based, at least in part, on one of the optional PCR value and the surrogate PCR value.

14. A computer-readable storage medium carrying one or more sequences of one or more instructions which, when executed by one or more processors, cause an apparatus to at least perform the following:
determine to generate a data packet carrier comprising an optional program clock reference (PCR) value, a variable delay reference (VDR) value, and a validity indicator;
process the data packet carrier to determine whether the data packet carrier comprises the optional PCR value;
in response to the data packet carrier not comprising the optional PCR value then generating a surrogate PCR value;
determine if a media access control retry bit value indicates one of the optional PCR value and a surrogate PCR value is valid;
in response to a validity indication then causing, at least in part, the data packet carrier to be communicated based, at least in part, on the media access control retry bit value;
in response to an invalidity indication then causing, at least in part, one of the optional PCR value and the surrogate PCR value to be discarded;
wherein the surrogate PCR value is generated remotely by a graphics processing unit.

15. A computer-readable storage medium of claim 14 , wherein the apparatus is caused to:
determining a value of the validity indicator indicates one of the optional PCR value and the surrogate PCR value is valid; causing, at least in part, the value of the validity indicator to change to indicate one of the optional PCR value and the surrogate PCR value is invalid; and causing, at least in part, one of the optional PCR value and the surrogate PCR value to be discarded based, at least in part, on the changed value of the validity indicator;
causing, at least in part, a phase-locked loop to lock the surrogate PCR value to a clock of the graphics processing unit.

Assignees

• Li Guoqing
• Bennett Joseph A
• Prat Gideon
• Trainin Solomon B
• Lee Sang-Hee
• Somayazulu Vallabhajosyula Z
• Hayek George R
• Brouillette Pat
• Loukianov Dmitrii A
• Intel Corp

Inventors

• Li Guoqing
• Bennett Joseph A
• Prat Gideon
• Trainin Solomon B
• Lee Sang-Hee
• Somayazulu Vallabhajosyula Z
• Hayek George R
• Brouillette Pat
• Loukianov Dmitrii A

Classifications

• H04N21/6131

  involving transmission via a mobile phone network (wireless downlink channel access H04W74/006) · CPC title

• H04N21/4305

  Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets (arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083) · CPC title

• H04N21/23608

  Remultiplexing multiplex streams, e.g. involving modifying time stamps or remapping the packet identifiers · CPC title

• H04N21/242 Primary

  Synchronisation processes, e.g. processing of PCR [Programme Clock References] {(arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18)} · CPC title