Embedded clock in communication system

Patent metadata

Field	Value
Publication number	US-9722824-B2
Application number	US-201514985254-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Dec 30, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion.

First claim

What is claimed is:

1. A method for simultaneously transmitting data bits and a clock signal, the method comprising converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter, the clock signal being the most significant bit of the digital-to-analog conversion and the data bits being the least significant bit of the digital-to-analog conversion;
wherein a state of the clock signal is indicated by a polarity of the analog voltages.

2. A method for simultaneously transmitting data bits and a clock signal, the method comprising converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter, the clock signal being the most significant bit of the digital-to-analog conversion and the data bits being the least significant bit of the digital-to-analog conversion;
wherein logic one clock signals are converted to positive analog voltages and wherein logic zero clock signals are converted to negative analog voltages.

3. The method of claim 2 , wherein:
logic one data signals are converted to analog voltages greater than a first threshold when the clock signals are logic one; and
logic zero data signals are converted to analog voltages less than a second threshold when the clock signals are logic zero.

4. The method of claim 3 , wherein the first threshold is approximately two thirds the value of a maximum positive output of the digital-to-analog converter, and wherein the second threshold is approximately two thirds the value of a minimum negative output of the digital-to-analog converter.

5. A method for simultaneously transmitting data bits and a clock signal, the method comprising converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter, the clock signal being the most significant bit of the digital-to-analog conversion and the data bits being the least significant bit of the digital-to-analog conversion;
wherein:
logic zero data signals are converted to analog voltages between zero and a first threshold when the clock signals are logic one; and
logic one data signals are converted to analog voltages between zero and a second threshold when the clock signals are logic zero.

6. The method of claim 5 , wherein the first threshold is approximately two thirds the value of a maximum positive output of the analog-to-digital converter, and wherein the second threshold is approximately two thirds the value of a minimum negative output of the analog-to-digital converter.

7. A method for simultaneously transmitting data bits and a clock signal, the method comprising converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter, the clock signal being the most significant bit of the digital-to-analog conversion and the data bits being the least significant bit of the digital-to-analog conversion;
wherein:
logic one data signals are converted to analog voltages greater than a first threshold when the clock signals are logic one;
logic zero data signals are converted to analog voltages between zero and the first threshold when the clock signals are logic one;
logic one data signals are converted to analog voltages between zero and a second threshold when the clock signals are logic zero; and
logic zero data signals are converted to analog voltages less than the second threshold when the clock signals are logic zero.

8. A transmitter for generating a clock signal embedded in a data signal, the transmitter comprising:
a digital-to-analog converter (DAC) having an input for receiving a digital signal, the input including a most significant bit (MSB) input and a least significant bit (LSB) input;
the MSB being coupled to a clock input for receiving the clock signal;
the LSB being coupled to a data input for receiving the data signal;
the DAC having an analog output for outputting voltages in response to the signals at the MSB input and the LSB input;
wherein the DAC outputs a voltage of a first polarity when the clock signal is a logic one, and wherein the DAC outputs a voltage of a second polarity when the clock signal is a logic zero.

9. A transmitter for generating a clock signal embedded in a data signal, the transmitter comprising:
a digital-to-analog converter (DAC) having an input for receiving a digital signal, the input including a most significant bit (MSB) input and a least significant bit (LSB) input;
the MSB being coupled to a clock input for receiving the clock signal;
the LSB being coupled to a data input for receiving the data signal;
the DAC having an analog output for outputting voltages in response to the signals at the MSB input and the LSB input;
wherein the output voltage ranges from a positive maximum amplitude and a negative minimum amplitude, wherein the output voltage includes values of positive one third the positive maximum amplitude and one third the negative minimum amplitude.

Assignees

• Texas Instruments Inc

Inventors

• Payne Robert Floyd

Classifications

• H04L7/042

  Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15) · CPC title

• H04L25/4927 Primary

  using levels matched to the quantisation levels of the channel · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title